Microchip Technology AT28LV64B-25TC

Overview

AT28LV64B-25TC from Atmel is a 64 Kbit (8K × 8) low-voltage parallel EEPROM with software and hardware data protection, 250 ns read access time, 10 ms maximum page write cycle, and JEDEC-standard byte-wide pinout in 28-lead TSOP package. It operates from a single 3.3 V ±10% supply, draws 15 mA active current and 20 µA CMOS standby current, and supports industrial temperature range (–40°C to +85°C) for embedded control and firmware storage applications.

For engineers reviewing the AT28LV64B-25TC datasheet, AT28LV64B-25TC pinout, AT28LV64B-25TC application, or AT28LV64B-25TC equivalent, key selection criteria include page-write capability (1–64 bytes), DATA polling/toggle-bit write completion detection, 100,000 endurance cycles, 10-year data retention, and compatibility with static RAM-like bus interface timing.

Technical Context

The AT28LV64B-25TC implements a parallel EEPROM architecture with internal 64-byte page latching and autonomous internal control timer for self-timed write operations. Its dual-line chip enable (CE) and output enable (OE) logic enables flexible bus contention management in microcontroller-based systems without external glue logic.

It integrates both hardware-level write inhibition (VCC power-on delay, noise filtering on WE/CE, and signal-level gating) and software data protection (SDP) requiring a three-byte command sequence (0xAA, 0x55, 0xA0 at addresses 0x5555, 0x2AAA, 0x5555) before any write-ensuring robust immunity to power-up/down glitches and system noise.

Key Specifications

Pinout & Package

AT28LV64B-25TC is housed in a 28-lead Plastic Thin Small Outline Package (TSOP), JEDEC MO-153 compliant, with 0.55 mm lead pitch and body dimensions 11.8 × 7.6 mm. Pin 1 is marked by index notch; pins 1 and 17 are NC (No Connect) per PLCC variant but not applicable to TSOP.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with AT28LV64B-25TC, AT28C64B-25JC demands higher supply voltage and lacks low-power standby, while MN63F6408APZ trades parallel simplicity for serial footprint savings-making AT28LV64B-25TC optimal for 3.3 V, bus-timing-critical, and firmware-update-intensive applications.

Availability

AT28LV64B-25TC is available at Aetrix Electronics and suitable for industrial PLC firmware storage, medical device configuration memory, and telecom line card bootloader storage requiring stable component supply, long-lifecycle support, and guaranteed industrial temperature performance.

Supply support for AT28LV64B-25TC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for industrial, automotive, and consumer applications.

The AT28LV64B product line delivers low-voltage, page-write-capable parallel EEPROMs designed for reliable firmware and configuration storage in resource-constrained embedded systems where SRAM-like interface simplicity and robust data integrity are critical.

FAQ

What is the maximum read access time specified for the AT28LV64B-25TC?

The AT28LV64B-25TC has a maximum read access time of 250 ns, measured from address valid or CE/OE assertion to valid data on I/O0–I/O7. This specification applies across the full industrial temperature range (–40°C to +85°C) and 3.3 V ±10% supply, ensuring deterministic timing for 4 MHz bus systems. The "25" in the part number explicitly denotes this 250 ns speed grade.

Does the AT28LV64B-25TC require external circuitry for write protection?

No, the AT28LV64B-25TC integrates both hardware and software data protection without external components. Hardware protection includes VCC power-on delay, noise filtering on WE/CE inputs, and signal-level gating. Software Data Protection (SDP) requires a three-byte unlock sequence (0xAA, 0x55, 0xA0) before any write-making external write-protect pins or jumpers unnecessary for most implementations of AT28LV64B-25TC.

How does page write operation work in the AT28LV64B-25TC?

The AT28LV64B-25TC supports page write of 1–64 bytes using an internal 64-byte latch. After initiating a write with the SDP sequence, the host loads bytes sequentially within 100 µs intervals; A6–A12 define the target page, while A0–A5 select individual bytes. Once the final byte is latched, the device automatically executes the internal 10 ms programming cycle-freeing the bus for other tasks during write execution in AT28LV64B-25TC.

Can the AT28LV64B-25TC be used in place of a standard EPROM like the 27C64?

No-the AT28LV64B-25TC is not a direct replacement for UV-erasable EPROMs such as the 27C64. While it shares JEDEC byte-wide pinout compatibility, it requires different write protocols (SDP sequence, no VPP voltage), operates at 3.3 V (not 5 V or 12.5 V), and uses electrical erase/write instead of UV erasure. Direct substitution would require firmware and power supply modifications for AT28LV64B-25TC integration.

What package type is used for the AT28LV64B-25TC?

The AT28LV64B-25TC uses a 28-lead Plastic Thin Small Outline Package (TSOP), designated as package code "28T" per Atmel's ordering information. It conforms to JEDEC MO-153, features gull-wing leads, 0.55 mm pitch, and body dimensions of 11.8 mm × 7.6 mm-optimized for surface-mount assembly in space-constrained industrial PCBs using AT28LV64B-25TC.