Microchip Technology AT28LV64B-25TI
- Part No.:
- AT28LV64B-25TI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-TSSOP (0.465", 11.80mm Width)
- Datasheet:
-
AT28LV64B-25TI.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28TSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28LV64B-25TI from Atmel is a 64K-bit (8K × 8) parallel EEPROM with 3.3V ±10% single-supply operation, 250 ns read access time, and hardware/software data protection. It supports page write (1–64 bytes), DATA polling, and toggle-bit write completion detection for embedded control and firmware storage in industrial temperature range (−40°C to +85°C).
For engineers reviewing the AT28LV64B-25TI datasheet, AT28LV64B-25TI pinout, AT28LV64B-25TI application, or AT28LV64B-25TI equivalent, key selection criteria include JEDEC byte-wide pin compatibility, 100,000 write endurance, 10-year data retention, low 20 µA CMOS standby current, and software data protection (SDP) command sequence requirement.
Technical Context
The AT28LV64B-25TI operates as a static RAM-compatible nonvolatile memory: reads require CE and OE low with WE high; writes initiate on falling edge of CE or WE with OE high. Its internal 64-byte page register latches address and data, enabling burst loading before autonomous internal programming.
Write completion is verified via I/O7 DATA polling (complement-to-data then true data) or I/O6 toggle-bit behavior. Software Data Protection mandates a three-byte command sequence (0xAA→0x55→0xA0 at addresses 0x5555, 0x2AAA, 0x5555) before each write cycle, preventing inadvertent writes during power transitions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), organized as byte-addressable parallel EEPROM |
| Read Access Time | 250 ns max - determines minimum bus cycle timing for CPU or controller interface |
| Page Write Cycle | 10 ms max - defines worst-case latency for 64-byte firmware update block |
| Endurance | 100,000 write/erase cycles - supports field-upgradable systems with frequent configuration updates |
| Data Retention | 10 years at 85°C - ensures long-term reliability in industrial environments without refresh |
| Supply Voltage | 3.3 V ±10% - compatible with modern low-voltage logic families and eliminates level-shifting needs |
| Standby Current | 20 µA (CMOS) - enables ultra-low-power operation in battery-backed or energy-constrained systems |
Pinout & Package
AT28LV64B-25TI is available in 28-lead TSOP (28T) package per JEDEC MS-013, with 0.55 mm lead pitch and 11.8 × 8.0 mm body size. Pin functions are JEDEC-standard byte-wide parallel interface.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus (8K locations); A6–A12 define page boundaries for 64-byte page writes |
| I/O0–I/O7 | Bidirectional Data Bus | Byte-wide data path; I/O7 used for DATA polling, I/O6 for toggle-bit write status |
| CE | Chip Enable | Active-low chip select; must be low for read/write; high disables outputs and inhibits writes |
| OE | Output Enable | Active-low output control; enables data bus drivers during read; high forces high-impedance state |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; high inhibits all write operations |
| VCC | Power Supply | +3.3 V ±10% supply; powers core logic and memory array; includes internal power-on delay |
| GND | Ground | Reference return for all signals and power; decoupling required within 1 cm of VCC pin |
| NC | No Connect | Unbonded pins (TSOP pins 1, 14, 28); must remain unconnected per datasheet |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection (SDP) | Three-byte unlock sequence prevents accidental writes during power-up/down or noise events |
| Hardware Write Inhibit | Automatic 10 ms VCC power-on delay plus OE/CE/WE logic-level inhibition blocks spurious writes |
| Page Write Operation | Internal 64-byte latch allows burst loading and autonomous programming-reduces host CPU overhead |
| DATA Polling & Toggle Bit | Dual asynchronous write-completion detection methods eliminate need for fixed delays or timers |
| JEDEC Byte-wide Pinout | Direct drop-in replacement for industry-standard 27C64/28C64 EPROMs and EEPROMs in existing designs |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
|
Use Scenario: Storing runtime-configurable I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers operating continuously at 85°C ambient. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via 8-bit parallel bus; retains settings across cold starts and brownouts. Use Value: 10-year data retention and 100,000-cycle endurance ensure calibration integrity over full product lifecycle without maintenance. |
Use Scenario: Holding factory-calibrated sensor offsets and gain coefficients in portable diagnostic equipment requiring FDA-compliant traceability. IC Role / Device Role / Timing Role: Secure parameter storage with SDP-enabled write protection to prevent unauthorized modification of medical calibration data. Use Value: Hardware+software write protection guarantees data integrity during transport, sterilization, and clinical use. |
| Telecom Base Station Boot Code | Automotive Body Control Module (BCM) |
|
Use Scenario: Storing boot loader and FPGA configuration bitstreams in outdoor telecom cabinets exposed to −40°C to +85°C thermal cycling. IC Role / Device Role / Timing Role: Parallel EEPROM providing fast 250 ns read access for ROM-based boot initialization sequences. Use Value: Industrial temperature rating and 3.3V-only operation simplify power design versus 5V legacy EEPROMs. |
Use Scenario: Recording door lock actuator learning positions, window auto-up/down limits, and lighting profiles in automotive BCMs. IC Role / Device Role / Timing Role: Field-updatable nonvolatile memory supporting dealer reprogramming and end-user personalization. Use Value: Page write capability enables efficient multi-byte updates without erasing entire sectors or requiring external buffers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-25JI | 5V-only supply (4.5–5.5V); no low-voltage operation; identical 64K×8 organization and JEDEC pinout | Requires separate 5V rail; unsuitable for 3.3V-only systems or mixed-voltage designs with level shifters | Select when legacy 5V infrastructure exists and voltage translation is undesirable |
| MN63C64-25PL | Same 3.3V supply and 250 ns access; 10,000-cycle endurance; no software data protection feature | Lacks SDP command sequence; relies solely on hardware write inhibit, increasing risk of corruption during power transients | Choose only in cost-sensitive, low-write-frequency applications where SDP is not mandated |
Compared with AT28LV64B-25TI, AT28C64B-25JI requires higher voltage and lacks low-power benefits, while MN63C64-25PL sacrifices write safety and endurance-making AT28LV64B-25TI optimal for robust, field-upgradable industrial systems.
Availability
AT28LV64B-25TI is available at Aetrix Electronics and suitable for industrial automation, medical instrumentation, and telecom infrastructure requiring stable component supply, long-term obsolescence management, and guaranteed industrial temperature performance.
Supply support for AT28LV64B-25TI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.
The AT28LV64B product line delivers low-voltage, high-reliability parallel EEPROMs designed for firmware storage, configuration retention, and calibration data logging in harsh industrial and automotive environments.
FAQ
What is the maximum operating temperature range for the AT28LV64B-25TI?
The AT28LV64B-25TI is rated for industrial temperature operation from −40°C to +85°C. This specification is confirmed in the Ordering Information table and DC Operating Range section of the datasheet, making it suitable for deployment in extended-temperature environments such as factory floors, outdoor telecom enclosures, and under-hood automotive modules where thermal stability is critical. The AT28LV64B-25TI maintains full functionality-including 250 ns read access and 10 ms page write-across this entire range.
Does the AT28LV64B-25TI require external high voltage for device identification memory access?
Yes, accessing the additional 64-byte device identification area (addresses 7FC0H–7FFFH) requires raising A9 to 12.0 V ± 0.5 V, as explicitly stated in the DEVICE IDENTIFICATION section. This high-voltage mode is separate from normal 3.3V operation and must be implemented with dedicated circuitry; standard read/write operations use only the 3.3V supply. The AT28LV64B-25TI does not integrate charge pumps or internal voltage multipliers for this function.
How does the Software Data Protection (SDP) mechanism work on the AT28LV64B-25TI?
The AT28LV64B-25TI implements SDP as a mandatory three-byte unlock sequence: write 0xAA to address 0x5555, then 0x55 to 0x2AAA, then 0xA0 to 0x5555. Only after this exact sequence is completed can subsequent byte or page writes proceed. Any incomplete or incorrect sequence triggers internal write timers but writes no data. This behavior is documented in the Software Data Protection and Write Algorithm sections, ensuring the AT28LV64B-25TI remains immune to spurious writes during system instability.
Can the AT28LV64B-25TI be used as a direct replacement for older 5V EEPROMs like the AT28C64B?
No-the AT28LV64B-25TI is not a direct replacement due to its 3.3V-only supply requirement (3.3V ±10%) versus the AT28C64B's 5V operation (4.5–5.5V). While both share identical JEDEC byte-wide pinouts and 64K×8 organization, mixing voltages risks damage or undefined behavior. The AT28LV64B-25TI requires proper 3.3V logic-level interfacing and cannot tolerate 5V inputs on address/data lines without level translation. Its pinout compatibility applies only within 3.3V system designs.
What are the valid package options for the AT28LV64B-25TI according to the official ordering information?
The AT28LV64B-25TI is specifically designated for the 28-lead TSOP (28T) package, as confirmed in the Valid Part Numbers and Ordering Information tables. Other variants like AT28LV64B-25JI use PLCC (32J) or PDIP (28P6), but the "TI" suffix exclusively denotes the TSOP industrial-grade version. The datasheet explicitly lists "AT28LV64B-25TI" under the 28T package row with industrial temperature range, and no other package is associated with this exact part number.
AT28LV64B-25TI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-TSSOP (0.465", 11.80mm Width)
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 250 ns
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSOP
AT28LV64B-25TI FAQ
1.How can I place an order for AT28LV64B-25TI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28LV64B-25TI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28LV64B-25TI reliable?
The price and inventory of AT28LV64B-25TI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28LV64B-25TI is usually 5 days.
3.What payment methods are accepted for AT28LV64B-25TI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28LV64B-25TI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28LV64B-25TI?
AT28LV64B-25TI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28LV64B-25TI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28LV64B-25TI?
For technical support, including AT28LV64B-25TI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28LV64B-25TI requirements.
6.How does Aetrix verify that AT28LV64B-25TI is sourced from the original manufacturer or authorized distributors?
All AT28LV64B-25TI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28LV64B-25TI meets industry standards.
7.What is the process for return or replacement of AT28LV64B-25TI?
All AT28LV64B-25TI units undergo pre-shipment inspection (PSI). If there is an issue with AT28LV64B-25TI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28LV64B-25TI part is unused and in its original packaging.
Return procedure for AT28LV64B-25TI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28LV64B-25TI Tags

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