My Inquiry
My Account
Microchip Technology AT29C256-90TC
- Part No.:
- AT29C256-90TC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-TSSOP (0.465", 11.80mm Width)
- Datasheet:
-
AT29C256-90TC.pdf
- Description:
- IC FLASH 256KBIT PARALLEL 28TSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,815
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT29C256-90TC from Atmel is a 256 Kbit (32K × 8) 5V-only Flash memory IC used for nonvolatile program/data storage in embedded microcontroller systems, industrial controllers, and legacy BIOS firmware. It delivers 90 ns read access time, supports page programming of 64-byte blocks, and operates across commercial temperature range (0°C to 70°C) in a 28-pin TSOP package.
For engineers reviewing the AT29C256-90TC datasheet, AT29C256-90TC pinout, AT29C256-90TC application, or AT29C256-90TC equivalent, key selection criteria include its 5V-only reprogramming capability, hardware/software data protection, DATA polling and toggle-bit end-of-write detection, and compatibility with standard SRAM bus interfaces without external voltage boosters.
Technical Context
The AT29C256-90TC implements a page-based Flash architecture where 64-byte pages are erased and programmed in a single internal cycle using on-chip timing control. Its command-set-driven operation-enabled by three-byte unlock sequences for software protection and product identification-eliminates need for high-voltage programming signals.
Read operations emulate static RAM behavior with dual-line chip enable (CE) and output enable (OE) control, while write cycles rely on precise WE/CE pulse timing (tWP ≥ 90 ns, tBLC ≤ 150 µs) and address latching via A0–A14. Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 256 Kbit (32,768 × 8), sufficient for firmware images or configuration tables in 8-bit microcontroller systems. |
| Read Access Time | 90 ns maximum - enables direct replacement of 90 ns SRAM or EPROM in legacy bus-timed designs. |
| Page Program Time | 10 ms per 64-byte page - allows rapid field updates without full-chip erase overhead. |
| VCC Supply | 5 V ± 10% - eliminates need for dedicated 12 V programming supply; compatible with standard logic rails. |
| Endurance | >10,000 write/erase cycles per sector - supports long-term field reprogramming in industrial logging or calibration applications. |
| Standby Current | 300 µA CMOS - enables low-power retention in battery-backed or energy-constrained systems. |
| Operating Temp | 0°C to 70°C - certified for commercial-grade embedded equipment including point-of-sale terminals and instrumentation. |
Pinout & Package
AT29C256-90TC is housed in a 28-lead Plastic Thin Small Outline Package (TSOP, Type I, package code 28T), measuring 8 mm × 13.4 mm with 0.55 mm lead pitch. Pin 1 is marked by a beveled corner; pins 1–14 and 15–28 occupy opposite long edges.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus supporting full 32K-word addressing; A0–A5 select byte within 64-byte page during programming. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; supports byte load, read, and DATA polling on I/O7/toggle on I/O6 during write cycles. |
| CE | Chip Enable | Active-low global device select; when high, forces outputs to high-impedance regardless of OE/WE state. |
| OE | Output Enable | Active-low read control; used with CE to prevent bus contention; must be high during programming. |
| WE | Write Enable | Active-low write control; initiates byte load or page program; requires precise 90 ns pulse width and 150 µs inter-byte timing. |
| VCC | Power Supply | +5 V ± 10% main supply; powers core logic and charge pump; VCC sense circuitry disables programming if below 3.8 V. |
| GND | Ground Reference | Signal and power return; decoupling capacitor required near VCC pin to suppress switching noise during page writes. |
Key Features
| Feature | Design Value |
|---|---|
| 5V-only reprogramming | Eliminates need for external 12 V programming voltage, simplifying system power design and reducing BOM count. |
| Internal page latches | 64-byte data and address latching frees host bus during 10 ms internal program cycle, enabling concurrent background tasks. |
| Hardware + software data protection | VCC sense, noise filtering, and three-byte unlock sequences prevent accidental writes during power-up, ESD events, or firmware glitches. |
| DATA polling & toggle-bit detection | I/O7 complement and I/O6 toggling provide real-time, bus-compatible status feedback without requiring timers or interrupts. |
| CMOS/TTL I/O compatibility | Supports direct interfacing with both 5 V CMOS and TTL logic families, easing integration into mixed-technology legacy systems. |
Applications
| Industrial PLC Firmware Storage | Legacy PC BIOS/UEFI Module |
|---|---|
Use Scenario: Storing ladder logic programs and I/O configuration maps in programmable logic controllers subject to frequent field updates. IC Role / Device Role / Timing Role: Nonvolatile firmware storage with in-system reprogrammability; replaces UV-erasable EPROMs requiring socket removal. Use Value: 10,000-cycle endurance and 10 ms page programming enable weekly firmware patches without hardware intervention or downtime. | Use Scenario: Holding boot firmware and hardware initialization code in desktop motherboards and embedded x86 platforms prior to UEFI transition. IC Role / Device Role / Timing Role: Boot ROM replacement with SRAM-like read interface and 90 ns access matching legacy chipset timing budgets. Use Value: 5V-only operation avoids need for charge-pump circuits, and DATA polling ensures reliable POST sequence synchronization. |
| Medical Device Calibration Data | Automated Test Equipment (ATE) Pattern Memory |
Use Scenario: Retaining sensor calibration coefficients and user-adjusted thresholds in portable diagnostic instruments with battery backup. IC Role / Device Role / Timing Role: Low-power nonvolatile data storage; leverages 300 µA standby current and software protection to prevent corruption during brownouts. Use Value: Hardware VCC-sense and software lock prevent unintended writes during power transitions, ensuring regulatory compliance for data integrity. | Use Scenario: Storing test vectors and pass/fail masks in semiconductor ATE systems requiring fast pattern loading and revision control. IC Role / Device Role / Timing Role: High-reliability pattern memory accessed as memory-mapped peripheral; uses page programming to update subsets without full reflash. Use Value: 90 ns read speed supports 11 MHz pattern clocking; 64-byte page granularity enables efficient mask edits between test runs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AM29F016B-90EC | 4 Mbit density, 90 ns access, 3 V/5 V tolerant, requires 12 V for programming. | Higher capacity but incompatible 12 V programming requirement; not drop-in for 5V-only systems. | Select only if system already provides 12 V and needs >256 Kbit storage. |
| SST39VF200A-90-4C-NHE | 2 Mbit density, 90 ns access, 3.3 V supply, no 5 V support, different command set. | Requires voltage translation and firmware adaptation; unsuitable for 5 V bus environments. | Choose only for new 3.3 V designs with migration path away from 5 V legacy infrastructure. |
Compared with AM29F016B-90EC and SST39VF200A-90-4C-NHE, the AT29C256-90TC uniquely satisfies strict 5V-only reprogramming, 256 Kbit capacity matching legacy footprint constraints, and full compatibility with existing SRAM-style bus protocols-making it the sole viable option for maintaining or repairing aging 5 V embedded systems without redesign.
Availability
AT29C256-90TC is available at Aetrix Electronics and suitable for industrial PLC firmware storage, legacy PC BIOS modules, and medical device calibration data retention requiring stable component supply and long-lifecycle support.
Supply support for AT29C256-90TC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.
The AT29C256 product line was designed for cost-sensitive, 5V-based embedded systems needing field-upgradable firmware storage without high-voltage programming infrastructure.
FAQ
What is the operating voltage range for AT29C256-90TC?
The AT29C256-90TC operates from a single 5 V supply with tolerance of ±10%, i.e., 4.5 V to 5.5 V. Its internal VCC sense circuit inhibits programming if voltage drops below ~3.8 V, and the device draws only 300 µA in CMOS standby mode at nominal VCC. This 5V-only specification makes AT29C256-90TC compatible with legacy logic rails and eliminates need for auxiliary programming voltages.
How does AT29C256-90TC detect completion of a page program cycle?
The AT29C256-90TC supports two hardware-supported methods: DATA polling on I/O7 (complement of last loaded byte indicates ongoing program; true data indicates completion) and toggle-bit detection on I/O6 (bit toggles during programming and stabilizes upon finish). Both methods allow the host system to poll asynchronously without timers or interrupts. These mechanisms are integral to AT29C256-90TC's in-system reprogrammability and ensure deterministic timing for subsequent read or write operations.
Can AT29C256-90TC replace standard SRAM in an existing design?
AT29C256-90TC can replace SRAM for read operations due to identical pinout, timing (90 ns access), and bus interface (CE/OE/WE control), but it cannot function as volatile RAM because writes require page-level programming and erase cycles. For read-mostly applications like boot code storage, AT29C256-90TC serves as a direct drop-in; however, any write path must be redesigned to implement the 64-byte page load sequence and polling logic required by AT29C256-90TC's Flash architecture.
What package type is used for AT29C256-90TC?
AT29C256-90TC uses a 28-lead Plastic Thin Small Outline Package (TSOP, Type I), designated as package code 28T. Its dimensions are 8 mm × 13.4 mm with 0.55 mm lead pitch and gull-wing leads. This surface-mount package supports automated PCB assembly and offers better thermal performance and smaller footprint than the PDIP or PLCC variants of the same device family.
Does AT29C256-90TC support both commercial and industrial temperature ranges?
No - the AT29C256-90TC is specified only for the commercial temperature range of 0°C to 70°C. Industrial-range versions carry the suffix "-90TI" (TSOP) or "-90JI" (PLCC). The "TC" suffix explicitly denotes the commercial-grade TSOP variant; using AT29C256-90TC outside 0°C–70°C may result in parametric failure or reduced endurance, as thermal characterization and screening are limited to that range.
AT29C256-90TC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-TSSOP (0.465", 11.80mm Width)
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSOP
AT29C256-90TC FAQ
1.How can I place an order for AT29C256-90TC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT29C256-90TC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT29C256-90TC reliable?
The price and inventory of AT29C256-90TC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT29C256-90TC is usually 5 days.
3.What payment methods are accepted for AT29C256-90TC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT29C256-90TC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT29C256-90TC?
AT29C256-90TC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT29C256-90TC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT29C256-90TC?
For technical support, including AT29C256-90TC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT29C256-90TC requirements.
6.How does Aetrix verify that AT29C256-90TC is sourced from the original manufacturer or authorized distributors?
All AT29C256-90TC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT29C256-90TC meets industry standards.
7.What is the process for return or replacement of AT29C256-90TC?
All AT29C256-90TC units undergo pre-shipment inspection (PSI). If there is an issue with AT29C256-90TC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT29C256-90TC part is unused and in its original packaging.
Return procedure for AT29C256-90TC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT29C256-90TC Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
