Microchip Technology AT34C02D-XHMHL-T
- Part No.:
- AT34C02D-XHMHL-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT34C02D-XHMHL-T.pdf
- Description:
- IC EEPROM 2KBIT I2C 1MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,363
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT34C02D-XHMHL-T from Microchip Technology (formerly Atmel) is a JEDEC EE1002/EE1002A-compliant Serial Presence Detect (SPD) EEPROM for DDR/DDR2/DDR3 DIMM modules, delivering 2 Kbit (256 × 8) nonvolatile memory with I²C-compatible 2-wire interface, 1.7–5.5 V operation, and hardware/software write protection. It supports 400 kHz (1.7–3.6 V) and 1 MHz (5.0 V) clock rates and features 16-byte page writes.
For engineers reviewing the AT34C02D-XHMHL-T datasheet, AT34C02D-XHMHL-T pinout, AT34C02D-XHMHL-T application, or AT34C02D-XHMHL-T equivalent, this device is selected for SPD memory in memory module design, low-voltage industrial systems, and applications requiring permanent/reversible software write protection plus hardware WP pin control.
Technical Context
The AT34C02D-XHMHL-T implements a dedicated SPD EEPROM architecture compliant with JEDEC EE1002 and EE1002A standards, enabling direct integration into DDR/DDR2/DDR3 memory module management. Its internal organization comprises 16 pages of 16 bytes each, supporting both byte and 16-byte page writes with automatic address incrementing within pages.
Write protection operates via three independent mechanisms: hardware-level inhibition via the WP pin (VCC = full-array lock), permanent software lock of lower 128 bytes (0x00–0x7F), and reversible software lock of the same region-each configurable without PCB changes. All protections coexist and are validated under -40°C to +85°C industrial temperature range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2,048 bits (256 × 8), organized as 16 pages × 16 bytes - enables SPD data storage for DDR/DDR2/DDR3 module configuration. |
| Supply Voltage | 1.7 V to 5.5 V - supports wide-range host system power rails including 1.8 V, 2.5 V, 3.3 V, and 5 V DIMM platforms. |
| I²C Speed | 400 kHz at 1.7–3.6 V; 1 MHz at 5.0 V - ensures compatibility with standard and high-speed SPD read cycles during system boot. |
| Write Endurance | 1,000,000 cycles - guarantees reliable field updates for SPD parameter reprogramming across product lifecycle. |
| Data Retention | 100 years at 25°C - maintains SPD configuration integrity over extended deployment without refresh. |
| Write Cycle Time | ≤5 ms maximum - defines minimum inter-write interval; critical for burst SPD initialization sequences. |
| Operating Temp | -40°C to +85°C - qualified for industrial-grade memory module environments including server and telecom applications. |
Pinout & Package
AT34C02D-XHMHL-T is packaged in an 8-lead TSSOP (Package Code: X, 4.4 mm body width), with lead finish NiPdAu, green/halogen-free construction, and industrial temperature grade (-40°C to +85°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A2 | Hardware Device Address Inputs | Enable up to eight AT34C02D devices on one I²C bus; hardwired to GND/VCC per JEDEC SPD addressing scheme. |
| GND | Ground Reference | Return path for VCC and signal logic; must be low-impedance to ensure noise-immune SPD communication. |
| SDA | Serial Data Line (Bidirectional, Open-Drain) | Shared I²C bus line; requires external pull-up; supports wire-OR with other open-drain devices on same bus. |
| SCL | Serial Clock Input | Master-generated clock; positive-edge sampling for input, negative-edge output timing per I²C protocol. |
| WP | Hardware Write Protect Control | Pull to VCC to disable all writes regardless of software protection state; floating or GND enables software-configurable protection. |
| VCC | Power Supply Input | Accepts 1.7–5.5 V; powers internal HV pump for EEPROM programming; decoupling capacitor required per JEDEC SPD layout guidelines. |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC EE1002/EE1002A SPD Compliance | Fully satisfies DDR/DDR2/DDR3 DIMM serial presence detect requirements - eliminates need for custom SPD firmware or translation logic. |
| Dual Software Write Protection | Permanent lock (irreversible) + reversible lock for lower 128 bytes - enables secure factory-programmed SPD fields while allowing field-updatable parameters. |
| Hardware WP Pin | Full-array write inhibit when tied to VCC - provides fail-safe protection during system power-up or firmware update sequences. |
| Schmitt Trigger Inputs | Filters noise on SCL/SDA/A0–A2/WP - ensures robust operation in electrically noisy DIMM slots and high-density PCB layouts. |
| 16-Byte Page Write | Reduces SPD initialization time by up to 16× vs. byte writes - accelerates memory module detection and configuration loading. |
Applications
| DDR3 DIMM Configuration Storage | Server Memory Module SPD |
|---|---|
Use Scenario: Storing JEDEC-defined timing parameters, manufacturer ID, module capacity, and thermal sensor calibration data on DDR3 UDIMMs. IC Role / Device Role / Timing Role: Dedicated SPD EEPROM providing standardized I²C-accessible configuration data to memory controller during POST. Use Value: Enables plug-and-play compatibility across vendor-neutral DDR3 platforms with guaranteed JEDEC compliance and 100-year data retention. |
Use Scenario: Supporting multi-rank RDIMM/LRDIMM modules in enterprise servers where SPD data must survive repeated thermal cycling and long-term storage. IC Role / Device Role / Timing Role: Nonvolatile SPD memory with industrial temp rating (-40°C to +85°C) and 1M endurance for field-serviceable memory upgrades. Use Value: Eliminates risk of SPD corruption during hot-swap events or firmware updates due to dual software lock + hardware WP protection. |
| DDR2 Memory Subsystem Calibration | Industrial Embedded Memory Modules |
Use Scenario: Holding DDR2-specific CAS latency, tRCD, tRP, and voltage settings in industrial automation controllers with legacy DDR2 interfaces. IC Role / Device Role / Timing Role: JEDEC EE1002A-compliant SPD device ensuring correct memory initialization sequence for DDR2 SDRAM controllers. Use Value: Guarantees boot-time reliability in mission-critical systems where incorrect SPD reads cause system hang or data corruption. |
Use Scenario: Providing SPD-like configuration storage in ruggedized embedded memory modules used in transportation or energy infrastructure equipment. IC Role / Device Role / Timing Role: Low-voltage (1.7 V min) SPD EEPROM operating reliably across wide temperature swings and vibration-prone environments. Use Value: Supports extended product lifecycles with 100-year data retention and halogen-free NiPdAu TSSOP package for RoHS/REACH compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SPD EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C02D-MAHM-T | Same 2 Kbit density and I²C interface, but lacks JEDEC EE1002/EE1002A SPD compliance and permanent software write protection. | Intended for general-purpose EEPROM use, not certified for DDR/DDR2/DDR3 SPD function. | Select only if SPD compliance is unnecessary and cost sensitivity outweighs JEDEC certification requirements. |
| STTS222B-TR | Integrated temperature sensor + 2 Kbit EEPROM in same TSSOP-8 package; no SPD compliance or software write protection features. | Targets thermal monitoring + basic NVM needs, not memory module SPD functionality. | Choose only when combined temperature sensing and non-SPD EEPROM are required in space-constrained designs. |
Compared with AT34C02D-XHMHL-T, AT24C02D-MAHM-T omits SPD-specific addressing, protection modes, and JEDEC validation - making it unsuitable for certified DIMM use. STTS222B-TR trades SPD capability for sensor integration, sacrificing SPD compliance and write protection for thermal telemetry.
Availability
AT34C02D-XHMHL-T is available at Aetrix Electronics and suitable for DDR3 DIMM manufacturing, server memory module refurbishment, and industrial embedded memory subsystems requiring stable component supply, long-lifecycle support, and JEDEC-compliant SPD functionality.
Supply support for AT34C02D-XHMHL-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full support for the AT34C02D family, offering long-term product availability, technical documentation, and industrial-grade qualification.
The AT34C02D series was designed specifically for JEDEC-compliant Serial Presence Detect in DDR/DDR2/DDR3 memory modules, emphasizing SPD protocol fidelity, write protection robustness, and wide-voltage interoperability.
FAQ
What is the primary application of the AT34C02D-XHMHL-T?
The AT34C02D-XHMHL-T is engineered exclusively for Serial Presence Detect (SPD) functionality in DDR, DDR2, and DDR3 Dual Inline Memory Modules (DIMMs). It stores JEDEC-standardized configuration data-including timing parameters, module capacity, and manufacturer information-that memory controllers read during system boot. Its AT34C02D-XHMHL-T implementation meets EE1002 and EE1002A specifications, ensuring interoperability across compliant DIMM platforms.
Does the AT34C02D-XHMHL-T support both permanent and reversible software write protection?
Yes, the AT34C02D-XHMHL-T implements two distinct software write protection modes: a permanent mode that irreversibly locks the lower 128 bytes (0x00–0x7F) after programming, and a reversible mode that allows dynamic enable/disable of protection for the same region using specific command sequences. Both modes operate independently of the hardware WP pin, and the AT34C02D-XHMHL-T datasheet confirms their coexistence and mutual exclusivity per access attempt.
What package type does the AT34C02D-XHMHL-T use, and what are its key mechanical attributes?
The AT34C02D-XHMHL-T uses an 8-lead TSSOP package (Package Code: X), measuring 4.4 mm body width with NiPdAu lead finish, green/halogen-free construction, and industrial temperature rating (-40°C to +85°C). Its ordering suffix "XHMHL-T" explicitly denotes TSSOP (X), industrial grade (H), NiPdAu finish (M), tape-and-reel packaging (T), and lead-free/halogen-free compliance (L). This matches Atmel's official ordering code structure in the AT34C02D datasheet Section 11.
How does hardware write protection work on the AT34C02D-XHMHL-T?
Hardware write protection on the AT34C02D-XHMHL-T is controlled by the WP pin: when pulled to VCC, it inhibits all write operations-including byte, page, and software protection register writes-regardless of software protection status. When WP is grounded or floating, software-based protection modes become active. The AT34C02D-XHMHL-T datasheet Table 4-1 and Section 8.1 confirm this behavior, and internal pull-down ensures safe default operation if WP is left unconnected.
Is the AT34C02D-XHMHL-T compatible with standard I²C buses operating at 1 MHz?
Yes, the AT34C02D-XHMHL-T supports 1 MHz I²C operation at VCC = 5.0 V, as specified in its datasheet Features section and AC Characteristics Table 5-4. At lower voltages (1.7–3.6 V), it operates up to 400 kHz. This dual-speed capability ensures compatibility with both legacy 400 kHz SPD readers and high-speed 1 MHz implementations in modern server platforms, and the AT34C02D-XHMHL-T pinout and timing diagrams validate full I²C protocol compliance.
AT34C02D-XHMHL-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 2Kbit
- Memory Organization:
- 256 x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
AT34C02D-XHMHL-T FAQ
1.How can I place an order for AT34C02D-XHMHL-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT34C02D-XHMHL-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT34C02D-XHMHL-T reliable?
The price and inventory of AT34C02D-XHMHL-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT34C02D-XHMHL-T is usually 5 days.
3.What payment methods are accepted for AT34C02D-XHMHL-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT34C02D-XHMHL-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT34C02D-XHMHL-T?
AT34C02D-XHMHL-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT34C02D-XHMHL-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT34C02D-XHMHL-T?
For technical support, including AT34C02D-XHMHL-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT34C02D-XHMHL-T requirements.
6.How does Aetrix verify that AT34C02D-XHMHL-T is sourced from the original manufacturer or authorized distributors?
All AT34C02D-XHMHL-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT34C02D-XHMHL-T meets industry standards.
7.What is the process for return or replacement of AT34C02D-XHMHL-T?
All AT34C02D-XHMHL-T units undergo pre-shipment inspection (PSI). If there is an issue with AT34C02D-XHMHL-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT34C02D-XHMHL-T part is unused and in its original packaging.
Return procedure for AT34C02D-XHMHL-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT34C02D-XHMHL-T Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
