Microchip Technology AT34C02D-XHM-T
- Part No.:
- AT34C02D-XHM-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT34C02D-XHM-T.pdf
- Description:
- IC EEPROM 2KBIT I2C 1MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,263
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT34C02D-XHM-T from Microchip Technology (formerly Atmel) is a JEDEC EE1002/EE1002A-compliant Serial Presence Detect (SPD) EEPROM for DDR/DDR2/DDR3 DIMM modules, providing 2,048-bit (256 × 8) I²C-compatible nonvolatile memory with 1.7V–5.5V operation, permanent/reversible software write protection for lower 128 bytes, and hardware write protection via WP pin.
For engineers reviewing the AT34C02D-XHM-T datasheet, AT34C02D-XHM-T pinout, AT34C02D-XHM-T application, or AT34C02D-XHM-T equivalent, this device delivers SPD-specific timing compliance, dual-layer write protection flexibility, page-write capability (16-byte), 1 MHz I²C support at 5V, and industrial-grade reliability (1M write cycles, 100-year retention) in an 8-lead TSSOP package.
Technical Context
The AT34C02D-XHM-T implements a dedicated SPD EEPROM architecture with hardwired A0–A2 address inputs enabling up to eight devices on one I²C bus, and supports both current-address and random-address read modes with sequential read capability. Its internal 16-page × 16-byte memory organization enables efficient byte and page writes with automatic address roll-over within pages.
Write protection is implemented through three independent mechanisms: hardware-level inhibition via WP pin (full-array lock when tied to VCC), irreversible software lock of addresses 0x00–0x7F, and reversible software lock of the same region using specific command sequences (0x62h/0x66h) with defined A-pin voltage conditions. All protections enforce tWR = 5 ms maximum self-timed write cycle.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2,048 bits (256 × 8), organized as 16 pages × 16 bytes - enables SPD data storage for DDR/DDR2/DDR3 module configuration. |
| Interface | I²C-compatible 2-wire serial interface - supports standard-mode (400 kHz @ 1.7V/2.5V) and fast-mode (1 MHz @ 5.0V) timing. |
| Supply Voltage | 1.7V to 5.5V - allows direct integration into diverse DIMM power domains without level-shifting. |
| Write Protection | Three-tiered: hardware (WP pin → full array), permanent software (lower 128 bytes, irreversible), reversible software (same region, programmable via 0x62h/0x66h). |
| Endurance & Retention | 1,000,000 write cycles and 100 years data retention - meets long-life requirements for server and industrial memory modules. |
| Package | 8-lead TSSOP (4.4 mm body width) - RoHS-compliant, lead-free NiPdAu finish, industrial temperature range (−40°C to +85°C). |
| AC Timing (tWR) | Maximum 5 ms write cycle time - defines minimum inter-write interval; independent of protection state. |
Pinout & Package
AT34C02D-XHM-T is supplied in an 8-lead plastic Thin Shrink Small Outline Package (TSSOP), 4.4 mm body width, with gull-wing leads and NiPdAu lead finish. Pin 1 is marked by a beveled corner or laser mark per JEDEC MO-153.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A2 | Hardware Device Address Inputs | Hardwired to GND/VCC to select one of eight possible I²C addresses (1010xxxR/W); floating defaults to GND but not recommended. |
| GND | Ground Reference | Primary return path for VCC and signal currents; must be low-impedance for noise immunity in DIMM SPD applications. |
| SDA | Serial Data Line | Bidirectional open-drain I²C data line; requires external pull-up; supports wire-OR with other I²C devices on same bus. |
| SCL | Serial Clock Input | Positive-edge clock input for data latching; negative-edge used for data output; defines I²C bus timing compliance. |
| WP | Hardware Write Protect Control | Active-high (VCC) disables all writes to entire memory; GND/floating enables software-controlled protection modes. |
| VCC | Power Supply | Single supply input (1.7V–5.5V); powers internal HV pump, logic, and EEPROM array; decoupling capacitor required. |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC EE1002/EE1002A SPD Compliance | Guarantees interoperability with DDR/DDR2/DDR3 memory controllers for standardized SPD data access and timing. |
| 16-byte Page Write with Partial Writes | Enables efficient multi-byte updates (e.g., SPD byte blocks) without requiring full-page erasure or external buffering. |
| Schmitt Trigger Filtered Inputs | Rejects noise on SCL/SDA/A0–A2/WP lines in electrically noisy DIMM environments, improving bus robustness. |
| Permanent + Reversible Software Write Protection | Allows secure locking of critical SPD fields (e.g., manufacturer ID, module type) while permitting field-updatable parameters. |
| Self-timed 5 ms Write Cycle | Eliminates need for external write timing control; ensures deterministic completion regardless of VCC or temperature. |
Applications
| DDR3 DIMM SPD Configuration | Server Memory Module Calibration |
|---|---|
|
Use Scenario: Storing JEDEC-defined SPD data (timings, density, vendor ID, thermal sensor info) on DDR3 UDIMMs for BIOS initialization. IC Role / Device Role / Timing Role: Dedicated SPD EEPROM interfacing directly with memory controller's I²C bus during boot sequence. Use Value: Ensures system compatibility and optimal memory training by delivering standardized, tamper-resistant configuration data. |
Use Scenario: Providing calibrated timing offsets and thermal derating parameters for high-reliability server memory subsystems. IC Role / Device Role / Timing Role: Nonvolatile storage of post-manufacturing calibration coefficients accessed during warm reset or runtime tuning. Use Value: Enables dynamic margining and lifetime thermal adaptation without requiring firmware reflash or external NVM. |
| Industrial DDR2 Memory Modules | Embedded Computing Memory Subsystems |
|
Use Scenario: Supporting extended-temperature DDR2 modules in factory automation controllers where SPD data must survive 10+ year deployments. IC Role / Device Role / Timing Role: Industrial-grade SPD EEPROM operating across −40°C to +85°C with guaranteed 100-year data retention. Use Value: Eliminates field failures due to SPD corruption in harsh environments, reducing maintenance and warranty costs. |
Use Scenario: Storing board-specific memory configuration (voltage, drive strength, termination) in compact embedded systems with space-constrained PCBs. IC Role / Device Role / Timing Role: Low-profile TSSOP-packaged SPD EEPROM minimizing footprint while maintaining full JEDEC compliance. Use Value: Reduces BOM count and layout complexity versus discrete EEPROM + level shifter solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SPD EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C02D-MAHM-T | Same 2K density and TSSOP-8 package, but lacks JEDEC EE1002/EE1002A SPD compliance and permanent software write protection. | General-purpose I²C EEPROM; unsuitable for DDR/DDR2/DDR3 SPD use due to missing SPD timing and register structures. | Select only for non-SPD applications requiring basic 2K EEPROM functionality in identical footprint. |
| STTS222B-TR | Integrated SPD EEPROM + temperature sensor in 8-lead TSSOP; shares same I²C address space but adds analog sensing circuitry. | Replaces discrete SPD EEPROM + external temp sensor; requires modified host firmware to read sensor registers alongside SPD data. | Choose when thermal monitoring is required alongside SPD - eliminates second component but increases firmware integration effort. |
Compared with AT24C02D-MAHM-T and STTS222B-TR, the AT34C02D-XHM-T uniquely satisfies JEDEC SPD timing and register map requirements while offering irreversible lower-half write protection - essential for certified DDR memory module designs where SPD integrity is mandatory.
Availability
AT34C02D-XHM-T is available at Aetrix Electronics and suitable for DDR3 DIMM manufacturing, server memory module calibration, and industrial DDR2 memory applications requiring stable component supply, long-term lifecycle support, and JEDEC-compliant SPD functionality.
Supply support for AT34C02D-XHM-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full product support, documentation, and qualification for legacy Atmel memory devices including the AT34C02D series.
The AT34C02D product line was designed specifically for JEDEC-compliant Serial Presence Detect in DDR/DDR2/DDR3 memory modules, emphasizing SPD timing accuracy, write-protection security, and industrial temperature resilience.
FAQ
What is the primary function of the AT34C02D-XHM-T in memory modules?
The AT34C02D-XHM-T serves as a JEDEC EE1002/EE1002A-compliant Serial Presence Detect (SPD) EEPROM in DDR/DDR2/DDR3 DIMMs. It stores standardized configuration data - including timings, density, vendor ID, and thermal parameters - that the memory controller reads during system boot to initialize and configure the DRAM. Its design ensures strict SPD timing compliance and reliable nonvolatile storage under industrial conditions. The AT34C02D-XHM-T is optimized for this exact role and is not intended as a general-purpose EEPROM.
Does the AT34C02D-XHM-T support I²C fast mode, and what voltage conditions apply?
Yes, the AT34C02D-XHM-T supports I²C fast mode at 1 MHz, but only when VCC is 5.0 V. At 1.7 V or 2.5 V, it operates in standard mode up to 400 kHz. This voltage-dependent speed scaling is explicitly specified in the datasheet and reflects internal timing constraints of the I²C interface logic. The AT34C02D-XHM-T maintains full protocol compliance across both modes, including tSU.STA, tHD.STA, and tBUF requirements per JEDEC and I²C specifications.
How does hardware write protection work on the AT34C02D-XHM-T, and can it be overridden?
Hardware write protection on the AT34C02D-XHM-T is controlled solely by the WP pin: when pulled to VCC, all write operations (including software protection register programming) are disabled, and the device responds with no ACK to any write command. This protection cannot be overridden by software or power cycling - it is strictly pin-driven and active regardless of software protection state. The AT34C02D-XHM-T enforces this behavior per Table 8-4 in the datasheet, ensuring unconditional lockout when WP = VCC.
What is the difference between permanent and reversible software write protection in the AT34C02D-XHM-T?
Permanent software write protection (PSWP), once enabled via command 0x60h, irreversibly locks addresses 0x00–0x7F - the lower 128 bytes - and cannot be cleared even after power loss. Reversible software write protection (RSWP) uses commands 0x62h (set) and 0x66h (clear) and requires specific A-pin voltage conditions (e.g., A0 = VHV); it protects the same 128-byte region but can be disabled. Both operate independently of the WP pin state unless WP = VCC, which overrides all software protection. The AT34C02D-XHM-T implements these two distinct mechanisms to meet SPD security requirements.
Which package type does the AT34C02D-XHM-T use, and what are its key mechanical features?
The AT34C02D-XHM-T uses an 8-lead TSSOP (Thin Shrink Small Outline Package) with 4.4 mm body width, gull-wing leads, and NiPdAu lead finish. Per ordering code "XHM", it conforms to JEDEC MO-153, has 0.65 mm lead pitch, and is rated for industrial temperature (−40°C to +85°C). The "H" denotes green/halogen-free construction and NiPdAu plating; "M" indicates 1.7V–5.5V operation. This package is pin-compatible with other Atmel 2K SPD EEPROMs in TSSOP, enabling drop-in replacement in existing DIMM layouts. The AT34C02D-XHM-T's mechanical drawing is documented as 8X in the datasheet.
AT34C02D-XHM-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 2Kbit
- Memory Organization:
- 256 x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
AT34C02D-XHM-T FAQ
1.How can I place an order for AT34C02D-XHM-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT34C02D-XHM-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT34C02D-XHM-T reliable?
The price and inventory of AT34C02D-XHM-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT34C02D-XHM-T is usually 5 days.
3.What payment methods are accepted for AT34C02D-XHM-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT34C02D-XHM-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT34C02D-XHM-T?
AT34C02D-XHM-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT34C02D-XHM-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT34C02D-XHM-T?
For technical support, including AT34C02D-XHM-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT34C02D-XHM-T requirements.
6.How does Aetrix verify that AT34C02D-XHM-T is sourced from the original manufacturer or authorized distributors?
All AT34C02D-XHM-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT34C02D-XHM-T meets industry standards.
7.What is the process for return or replacement of AT34C02D-XHM-T?
All AT34C02D-XHM-T units undergo pre-shipment inspection (PSI). If there is an issue with AT34C02D-XHM-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT34C02D-XHM-T part is unused and in its original packaging.
Return procedure for AT34C02D-XHM-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT34C02D-XHM-T Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
