Microchip Technology AT34C04-MA5M-E
- Part No.:
- AT34C04-MA5M-E
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-UFDFN Exposed Pad
- Datasheet:
-
AT34C04-MA5M-E.pdf
- Description:
- IC EEPROM 4KBIT I2C 1MHZ 8UDFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT34C04-MA5M-E from Microchip Technology (formerly Atmel) is a 4-Kbit I²C-compatible Serial EEPROM optimized for Serial Presence Detect (SPD) in DDR SDRAM modules. It provides 512 bytes × 8-bit memory, JEDEC JC42.4 (EE1004-v) compliance, 1.7V–3.6V operation, and reversible software write protection across four 128-byte quadrants - enabling secure storage of module timing, voltage, and configuration data.
For engineers reviewing the AT34C04-MA5M-E datasheet, AT34C04-MA5M-E pinout, AT34C04-MA5M-E application, or AT34C04-MA5M-E equivalent, key selection considerations include SPD protocol compatibility, FM+ I²C support up to 1 MHz, quadrant-level RSWP control, 1,000,000 write endurance, and UDFN-8 packaging for high-density DIMM layouts.
Technical Context
The AT34C04-MA5M-E implements a dual-halves memory architecture with Set Page Address (SPA) and Read Page Address (RPA) commands to maintain backward compatibility with legacy EE1002-based SPD systems while supporting full 4-Kbit capacity. Its internal address counter selects either lower (Quadrants 0–1) or upper (Quadrants 2–3) 256-byte halves via A0-driven high-voltage command sequences.
It uses Schmitt-triggered, noise-filtered SDA/SCL inputs, supports bus timeout (25–35 ms), and features open-drain I²C FM+ interface with 100 kHz / 400 kHz / 1 MHz clock rate support. Write operations use self-timed 5 ms cycles with ACK polling, and standby current is as low as 1.6 µA at 1.7 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 4096 bits (512 × 8), organized as four 128-byte quadrants for granular write protection |
| Supply Voltage | 1.7 V to 3.6 V - enables direct integration into DDR3/DDR4 module power rails without level shifting |
| I²C Interface | FM+ compatible up to 1 MHz - supports high-speed SPD readout during system boot without bus contention |
| Write Endurance | 1,000,000 cycles - ensures reliable field updates across multiple memory module reconfigurations |
| Data Retention | 100 years at +25°C - guarantees SPD data integrity over full product lifecycle including long-term storage |
| Package | 8-pad UDFN (8MA2), 2.0 mm × 1.6 mm × 0.55 mm - space-efficient footprint for edge-mounted DIMM placement |
| Write Protection | Reversible Software Write Protection (RSWP) per quadrant - allows selective lockdown of SPD critical fields (e.g., timing parameters) without hardware fusing |
Pinout & Package
AT34C04-MA5M-E is supplied in an 8-pad UDFN package (JEDEC MO-229, variant 8MA2) with exposed thermal pad (non-connected). Pin 1 is top-left corner (A0), and the bottom-side metal pad may be left floating or connected to GND for mechanical stability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Device Address / RSWP Control | LSB of 3-bit hardware address; driven to 7–10 V for SPA/RPA commands to select memory half or verify protection status |
| A1 | Device Address Input | Second LSB of I²C slave address (7-bit); sets unique device ID on shared SPD bus (up to 8 devices) |
| A2 | Device Address Input | MSB of 3-bit hardware address; enables multi-device SPD topology on single DIMM or motherboard |
| GND | Power Reference | System ground return path; required for stable I²C signaling and internal voltage regulation |
| VCC | Power Supply | 1.7–3.6 V core supply; powers EEPROM array, control logic, and I/O buffers - no external regulator needed |
| NC | No Connect | Unbonded die pad; electrically isolated - may be tied to GND for PCB mechanical reinforcement only |
| SCL | Serial Clock Input | Asynchronous I²C clock input with Schmitt trigger and 50 ns noise filter - tolerates slow edges and bus noise in DIMM environments |
| SDA | Serial Data I/O | Open-drain bidirectional data line; requires external pull-up (≤8 kΩ); supports wire-OR with other SPD devices |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC JC42.4 (EE1004-v) Compliance | Fully satisfies SPD specification for DDR3/DDR4 modules - enables plug-and-play compatibility with standard memory controllers and BIOS |
| Reversible Software Write Protection (RSWP) | Per-quadrant enable/disable via software command - eliminates need for one-time-programmable fuses while preventing accidental SPD corruption |
| Legacy EE1002 Compatibility | Protocol-level support for 2-Kbit SPD systems - allows AT34C04-MA5M-E to replace older devices without firmware changes |
| Bus Timeout Protection | Auto-release of SDA after 25–35 ms SCL low time - prevents system lockup during I²C bus contention or controller fault |
| Low-Power Standby | 1.6 µA max at 1.7 V - minimizes quiescent current draw on DIMM VDDQ rail during system sleep states |
Applications
| DDR4 Server Memory Modules | DDR3 Laptop SO-DIMMs |
|---|---|
|
Use Scenario: Storing JEDEC-defined SPD data (module size, CAS latency, tRCD, voltage) on registered DDR4 RDIMMs used in enterprise servers. IC Role / Device Role / Timing Role: Dedicated SPD EEPROM interfacing directly with memory controller's I²C bus during power-on initialization. Use Value: Enables automatic memory training and configuration without BIOS hardcoding - reduces qualification time and supports mixed-module configurations. |
Use Scenario: Providing SPD information for DDR3 SO-DIMMs in ultrabooks where board space and power are constrained. IC Role / Device Role / Timing Role: Low-voltage (1.7 V) serial EEPROM mounted adjacent to DRAM chips, communicating via I²C FM+ at 400 kHz during boot. Use Value: UDFN-8 package saves >40% board area vs. SOIC-8; 1.6 µA standby current extends battery life in suspend-to-RAM states. |
| Industrial DDR3L Memory Boards | Embedded DDR4 ECC Modules |
|
Use Scenario: Storing extended timing parameters and temperature-compensated settings for DDR3L modules operating from –40°C to +125°C. IC Role / Device Role / Timing Role: SPD device with guaranteed operation across industrial temperature range and robust noise immunity via Schmitt-triggered I/O. Use Value: 100-year data retention and 1M-cycle endurance ensure SPD reliability over 15+ year deployments in factory automation systems. |
Use Scenario: Holding error-correcting code (ECC) configuration metadata and module revision history for mission-critical DDR4 ECC memory in medical imaging equipment. IC Role / Device Role / Timing Role: Securely write-protected quadrant stores immutable ECC algorithm identifiers and calibration checksums. Use Value: RSWP allows locking Quadrant 3 (0x300–0x3FF) against field updates while permitting dynamic writes to other quadrants for runtime logs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Serial Presence Detect EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STMicroelectronics M24C04-RMN6TP | 4-Kbit I²C EEPROM, 1.7–5.5 V, SO8/TSSOP8 only; lacks SPA/RPA commands and quadrant-level RSWP | Supports generic EEPROM use but not JEDEC SPD-compliant page addressing or legacy EE1002 mode | Choose for non-SPD designs requiring wider voltage range and standard I²C interface without SPD-specific features |
| ON Semiconductor CAT24C04HU4I-GT3 | 4-Kbit I²C EEPROM, 1.7–5.5 V, UDFN-8; supports 1 MHz I²C but no SPA/RPA or RSWP - only block write protection | Compatible with basic SPD reads but cannot emulate legacy 2-Kbit behavior or provide per-quadrant lockdown | Choose when UDFN-8 footprint is mandatory and SPD functionality is limited to static parameter storage without runtime reconfiguration |
Compared with M24C04-RMN6TP and CAT24C04HU4I-GT3, the AT34C04-MA5M-E uniquely delivers JEDEC JC42.4 compliance, reversible quadrant write protection, and dual-halves memory addressing - making it the only drop-in solution for DDR3/DDR4 SPD upgrades requiring legacy interoperability and field-programmable security.
Availability
AT34C04-MA5M-E is available at Aetrix Electronics and suitable for DDR4 server memory modules, DDR3 laptop SO-DIMMs, and industrial DDR3L memory boards requiring stable component supply, long-term lifecycle support, and RoHS-compliant green packaging.
Supply support for AT34C04-MA5M-E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full technical and manufacturing continuity for the AT34C04 family. The company specializes in microcontrollers, analog, and memory solutions for industrial, automotive, and computing markets.
The AT34C04 product line was designed specifically for Serial Presence Detect in DRAM modules, delivering JEDEC-compliant, high-reliability EEPROM with advanced software protection for memory configuration data.
FAQ
What is the primary application of the AT34C04-MA5M-E?
The AT34C04-MA5M-E is engineered for Serial Presence Detect (SPD) in DDR3 and DDR4 memory modules. It stores standardized module parameters - including size, speed, voltage, data width, and timing - enabling automatic system configuration during boot. Its JEDEC JC42.4 compliance and legacy EE1002 compatibility make it ideal for both new designs and drop-in replacements in existing DIMM platforms.
Does the AT34C04-MA5M-E support I²C Fast-Mode Plus (FM+)?
Yes, the AT34C04-MA5M-E fully supports I²C Fast-Mode Plus with clock rates up to 1 MHz. This capability allows faster SPD data reads during system initialization, reducing boot latency in high-performance servers and workstations. Its SDA/SCL inputs include integrated Schmitt triggers and 50 ns noise filters to maintain signal integrity at higher frequencies.
How does the Reversible Software Write Protection (RSWP) work on the AT34C04-MA5M-E?
The AT34C04-MA5M-E implements RSWP at the quadrant level (four 128-byte blocks), allowing independent enable/disable via software command sequences. Each quadrant's protection status can be verified using the Read RSWP command. Protection is reversed only by issuing a specific unlock sequence - no hardware fuse or permanent lock exists, ensuring field-upgrade flexibility while preventing accidental writes.
What package type is used for the AT34C04-MA5M-E?
The AT34C04-MA5M-E uses an 8-pad UDFN package (JEDEC MO-229, variant 8MA2), measuring 2.0 mm × 1.6 mm × 0.55 mm. This compact, leadless footprint is optimized for edge-mounting on DDR4/DDR3 DIMMs and SO-DIMMs. The bottom thermal pad is unconnected and may be left floating or grounded solely for mechanical stability.
Is the AT34C04-MA5M-E compatible with legacy 2-Kbit SPD systems?
Yes, the AT34C04-MA5M-E maintains full protocol compatibility with JEDEC EE1002 (2-Kbit) SPD devices through its Set Page Address (SPA) and Read Page Address (RPA) commands. When SPA = 0, it emulates a 2-Kbit device accessing Quadrants 0–1 only - enabling seamless integration into legacy BIOS and memory controller firmware without modification.
AT34C04-MA5M-E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-UFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 3.6V
- Operating Temperature:
- -20°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-UDFN (2x3)
AT34C04-MA5M-E FAQ
1.How can I place an order for AT34C04-MA5M-E through Aetrix?
Please submit a Request for Quotation (RFQ) for AT34C04-MA5M-E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT34C04-MA5M-E reliable?
The price and inventory of AT34C04-MA5M-E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT34C04-MA5M-E is usually 5 days.
3.What payment methods are accepted for AT34C04-MA5M-E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT34C04-MA5M-E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT34C04-MA5M-E?
AT34C04-MA5M-E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT34C04-MA5M-E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT34C04-MA5M-E?
For technical support, including AT34C04-MA5M-E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT34C04-MA5M-E requirements.
6.How does Aetrix verify that AT34C04-MA5M-E is sourced from the original manufacturer or authorized distributors?
All AT34C04-MA5M-E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT34C04-MA5M-E meets industry standards.
7.What is the process for return or replacement of AT34C04-MA5M-E?
All AT34C04-MA5M-E units undergo pre-shipment inspection (PSI). If there is an issue with AT34C04-MA5M-E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT34C04-MA5M-E part is unused and in its original packaging.
Return procedure for AT34C04-MA5M-E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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