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Microchip Technology AT34C04-MA5M-T
- Part No.:
- AT34C04-MA5M-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-UFDFN Exposed Pad
- Datasheet:
-
AT34C04-MA5M-T.pdf
- Description:
- IC EEPROM 4KBIT I2C 1MHZ 8UDFN
- Quantity:
- Payment:
- Shipping:
Inventory:19,779
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Product details
Overview
AT34C04-MA5M-T from Microchip Technology (formerly Atmel) is a 4-Kbit I²C-compatible Serial EEPROM optimized for Serial Presence Detect (SPD) in DDR SDRAM modules. It features 512 bytes × 8-bit organization, JEDEC JC42.4 (EE1004-v) compliance, reversible software write protection across four 128-byte quadrants, and operates from 1.7V to 3.6V. Used to store module timing parameters, voltage, size, and data width on memory DIMMs.
For engineers reviewing the AT34C04-MA5M-T datasheet, AT34C04-MA5M-T pinout, AT34C04-MA5M-T application, or AT34C04-MA5M-T equivalent, key selection criteria include SPD compliance, FM+ I²C support up to 1 MHz, quadrant-level RSWP, 100-year data retention, and compatibility with legacy EE1002 systems via page-addressing mode.
Technical Context
The AT34C04-MA5M-T implements a dual-halves memory architecture with independent 2-Kbit sections, each subdivided into two 128-byte quadrants-enabling JEDEC EE1004-v SPD functionality while maintaining backward compatibility with EE1002. Its Set Page Address (SPA) and Read Page Address (RPA) commands control internal address counter positioning between lower (Quadrants 0–1) and upper (Quadrants 2–3) halves.
It uses an I²C Fast-Mode Plus (FM+) interface with Schmitt-triggered, noise-filtered SDA/SCL inputs, bus timeout (25–35 ms), and 2-wire software reset. The A0 pin supports overvoltage tolerance (up to 10 V) for RSWP activation, and all quadrants support individual reversible software write protection verified via dedicated read command.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 4096 bits (512 bytes), organized as four 128-byte quadrants for SPD-compliant modular data storage |
| Supply Voltage | 1.7V to 3.6V - enables direct integration into low-voltage DDR3/DDR4 DIMM power domains |
| I²C Speed | Up to 1 MHz (FM+) - supports high-throughput SPD reads during system boot without bus contention |
| Write Endurance | 1,000,000 cycles - sufficient for field-programmable SPD updates across full product lifecycle |
| Data Retention | 100 years at +25°C - guarantees long-term integrity of critical memory module configuration data |
| Write Cycle Time | ≤5 ms - enables fast SPD reprogramming during manufacturing or field service |
| Quadrant Protection | Individually reversible software write protection per 128-byte quadrant - allows selective locking of vendor-specific vs. user-modifiable SPD fields |
Pinout & Package
AT34C04-MA5M-T is packaged in an 8-pad UDFN (8MA2) with exposed thermal pad (non-connected). Pin functions are electrically identical across SOIC/TSSOP/UDFN variants.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Device Address / RSWP Enable | LSB of 3-bit hardware address; driven to ≥7 V to activate Reversible Software Write Protection sequence |
| A1 | Device Address | Second LSB of hardware I²C slave address (A2–A0); sets unique 7-bit address on shared bus |
| A2 | Device Address | MSB of hardware I²C slave address (A2–A0); enables up to eight devices on same I²C bus |
| GND | Power Reference | System ground return path; required for stable bias and noise immunity in SPD subsystems |
| VCC | Power Supply | 1.7–3.6 V supply input; powers EEPROM core and I²C interface; no external regulator needed |
| NC | No Connect | Unbonded die pad; may be left floating or tied to GND for mechanical stability or EMI reduction |
| SCL | Serial Clock Input | Asynchronous clock line from host controller; Schmitt-triggered with 50 ns noise filtering; min 10 kHz to avoid timeout |
| SDA | Serial Data I/O | Open-drain bidirectional bus line; requires external pull-up ≤8 kΩ; transmits ACK/NACK and SPD data |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC JC42.4 (EE1004-v) Compliance | Fully satisfies SPD specification for DDR3/DDR4 memory modules, including mandatory byte layout and checksum requirements |
| Reversible Software Write Protection (RSWP) | Per-quadrant enable/disable via software command - eliminates need for hardware WP pin or external logic in DIMM designs |
| Legacy EE1002 Compatibility | Supports SPA/RPA addressing to emulate 2-Kbit behavior - enables drop-in replacement in older DDR2 systems without firmware changes |
| Bus Timeout Protection | Auto-release of SDA after 25–35 ms SCL low - prevents system lockup during I²C bus faults or master failure |
| Low-Power Standby | ≤4.0 μA at 3.6 V - minimizes standby current draw in always-on memory subsystems |
Applications
| DDR4 DIMM SPD Storage | DDR3 Memory Module Configuration |
|---|---|
Use Scenario: Stores JEDEC-defined SPD data (timing, voltage, size, manufacturer ID) on unbuffered DDR4 UDIMMs during manufacturing and field updates. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed via I²C during system POST to configure memory controller timing parameters. Use Value: Enables plug-and-play memory compatibility and eliminates manual BIOS configuration; RSWP protects critical vendor fields from accidental overwrite. | Use Scenario: Provides SPD data for DDR3 SODIMMs used in laptops and embedded systems requiring JEDEC-compliant boot-time memory initialization. IC Role / Device Role / Timing Role: Serial EEPROM acting as SPD slave device on SMBus/I²C; responds to fixed 7-bit address 0x50 for standard DIMM slots. Use Value: Supports 100 kHz and 400 kHz I²C speeds - ensures reliable SPD reads even under noisy laptop power rail conditions. |
| Server Memory Module Calibration | Industrial DRAM Subsystem Validation |
Use Scenario: Stores extended SPD data (temperature sensors, RAS features, thermal throttling thresholds) on RDIMMs/LRDIMMs in enterprise servers. IC Role / Device Role / Timing Role: Dual-halves memory architecture allows separate storage of base SPD (lower half) and extended calibration data (upper half) using SPA commands. Use Value: Enables field-upgradable calibration tables without risking corruption of base SPD - critical for server firmware update safety. | Use Scenario: Validates DDR2/DDR3 memory subsystems in industrial controllers where extended temperature operation (–40°C to +125°C) and long-term data integrity are required. IC Role / Device Role / Timing Role: High-reliability EEPROM with 1M write cycles and 100-year retention - deployed in programmable logic-based memory test fixtures. Use Value: Guarantees SPD data persistence across 15+ year product lifecycles in railway or energy infrastructure applications. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C04C-SSHM-T | 4-Kbit I²C EEPROM, 1.7–5.5 V supply, no RSWP or SPA/RPA; lacks SPD-specific addressing and EE1004-v compliance | General-purpose storage only - not suitable for DDR SPD; no quadrant protection or legacy compatibility mode | Select only for non-SPD applications requiring wider VCC range and simpler command set |
| STTS2222DPY | 2-Kbit SPD EEPROM, JEDEC EE1004-v compliant, but no RSWP; supports only 100/400 kHz I²C, no FM+ 1 MHz mode | Limited to basic SPD use cases; cannot store extended calibration data due to smaller capacity and no upper-half addressing | Choose when cost sensitivity outweighs need for field-upgradable extended SPD or high-speed programming |
Compared with AT24C04C-SSHM-T and STTS2222DPY, the AT34C04-MA5M-T uniquely delivers SPD-compliant 4-Kbit storage with reversible quadrant protection and FM+ speed - making it the only option supporting both legacy EE1002 systems and modern DDR4 extended SPD requirements in a single footprint.
Availability
AT34C04-MA5M-T is available at Aetrix Electronics and suitable for DDR4 DIMM manufacturing, DDR3 memory module configuration, and server memory calibration requiring stable component supply, long-term obsolescence management, and JEDEC-compliant SPD functionality.
Supply support for AT34C04-MA5M-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full support for legacy Atmel serial EEPROM products. The company specializes in microcontrollers, analog, and memory solutions for industrial, automotive, and computing markets.
The AT34C04-MA5M-T belongs to Microchip's SPD-optimized Serial EEPROM product line, designed specifically for DDR memory module configuration and JEDEC JC42.4 compliance - targeting DIMM manufacturers and memory subsystem integrators.
FAQ
What is the memory organization of the AT34C04-MA5M-T?
The AT34C04-MA5M-T contains 4096 bits (512 bytes) of EEPROM organized into four 128-byte quadrants (0–3), split across two 2-Kbit halves. Each half supports independent addressing via Set Page Address (SPA) and Read Page Address (RPA) commands, enabling JEDEC EE1004-v SPD compliance and legacy EE1002 compatibility. This structure allows secure, modular storage of DDR module parameters.
Does the AT34C04-MA5M-T support I²C Fast-Mode Plus?
Yes, the AT34C04-MA5M-T fully supports I²C Fast-Mode Plus (FM+) with guaranteed operation up to 1 MHz. It also maintains backward compatibility with standard-mode (100 kHz) and fast-mode (400 kHz) I²C buses. The device incorporates Schmitt-triggered, filtered SDA and SCL inputs and requires a minimum SCL frequency of 10 kHz to prevent bus timeout activation.
How does Reversible Software Write Protection (RSWP) work on the AT34C04-MA5M-T?
RSWP on the AT34C04-MA5M-T allows individual 128-byte quadrants to be write-protected via software commands. Protection is enabled by driving the A0 pin to ≥7 V and issuing a specific command sequence. Each quadrant's protection status can be verified independently. Protection is reversible only through another dedicated software command - no hardware WP pin is required.
Is the AT34C04-MA5M-T compatible with legacy 2-Kbit SPD systems?
Yes, the AT34C04-MA5M-T supports legacy JEDEC EE1002 (2-Kbit) systems via its Set Page Address (SPA) command. When SPA = 0, only the lower 256 bytes (Quadrants 0–1) are accessible - emulating a 2-Kbit device. No firmware changes are needed, though the AT34C04-MA5M-T does not support Permanent Write Protection, a deprecated feature in EE1002.
What package type is used for the AT34C04-MA5M-T?
The AT34C04-MA5M-T uses an 8-pad UDFN package (8MA2) with dimensions 2.0 mm × 1.6 mm × 0.55 mm. The bottom thermal pad is not internally connected and may be left floating or tied to GND. This space-saving package meets RoHS, Pb-free, and halide-free requirements and is pin-compatible with the SOIC and TSSOP variants of the same device.
AT34C04-MA5M-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-UFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 3.6V
- Operating Temperature:
- -20°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-UDFN (2x3)
AT34C04-MA5M-T FAQ
1.How can I place an order for AT34C04-MA5M-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT34C04-MA5M-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT34C04-MA5M-T reliable?
The price and inventory of AT34C04-MA5M-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT34C04-MA5M-T is usually 5 days.
3.What payment methods are accepted for AT34C04-MA5M-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT34C04-MA5M-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT34C04-MA5M-T?
AT34C04-MA5M-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT34C04-MA5M-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT34C04-MA5M-T?
For technical support, including AT34C04-MA5M-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT34C04-MA5M-T requirements.
6.How does Aetrix verify that AT34C04-MA5M-T is sourced from the original manufacturer or authorized distributors?
All AT34C04-MA5M-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT34C04-MA5M-T meets industry standards.
7.What is the process for return or replacement of AT34C04-MA5M-T?
All AT34C04-MA5M-T units undergo pre-shipment inspection (PSI). If there is an issue with AT34C04-MA5M-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT34C04-MA5M-T part is unused and in its original packaging.
Return procedure for AT34C04-MA5M-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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