Microchip Technology AT34C04-SS5M-B
- Part No.:
- AT34C04-SS5M-B
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT34C04-SS5M-B.pdf
- Description:
- IC EEPROM 4KBIT I2C 1MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,216
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT34C04-SS5M-B from Microchip Technology (acquired Atmel) is a 4-Kbit I²C-compatible Serial EEPROM optimized for DRAM module Serial Presence Detect (SPD) applications. It delivers 512 bytes × 8-bit memory organization, JEDEC JC42.4 (EE1004-v) compliance, 1.7V–3.6V single-supply operation, and reversible software write protection across four 128-byte quadrants - enabling secure storage of module timing, voltage, and configuration data in DDR3/DDR4 DIMMs.
For engineers reviewing the AT34C04-SS5M-B datasheet, AT34C04-SS5M-B pinout, AT34C04-SS5M-B application, or AT34C04-SS5M-B equivalent, key selection criteria include SPD-compliant I²C Fast-Mode Plus (1 MHz) support, quadrant-level RSWP control, bus timeout resilience, Schmitt-trigger noise immunity, and compatibility with legacy EE1002 systems via page-addressing mode.
Technical Context
The AT34C04-SS5M-B implements a dual 2-Kbit memory architecture split into four independent 128-byte quadrants, each individually protected via Reversible Software Write Protection (RSWP) commands using A0 overvoltage signaling (up to 10 V). Its I²C FM+ interface supports 100 kHz, 400 kHz, and 1 MHz clock rates with integrated spike suppression filters and Schmitt-trigger inputs on SDA/SCL.
Communication relies on two distinct device address prefixes: '1010' (0xAh) for standard read/write operations and '0110' (0x6h) for page address control (SPA/RPA) and RSWP configuration. The device enters low-power standby after Stop conditions or power-up, drawing only 1.6–4.0 μA, and features a 25–35 ms bus timeout to prevent system lock-ups under SCL hold faults.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 4096 bits (512 × 8), organized as four 128-byte quadrants for granular SPD data partitioning |
| Supply Voltage | 1.7 V to 3.6 V - enables direct integration with DDR3/DDR4 module VDDQ rails without level shifting |
| I²C Speed | Up to 1 MHz (FM+) - supports high-speed SPD reads during system boot without bus contention delays |
| Write Endurance | 1,000,000 cycles - ensures reliable field updates of SPD tables across product lifecycle |
| Data Retention | 100 years at +25°C - guarantees long-term integrity of critical memory module identification parameters |
| Write Cycle Time | ≤5 ms max - enables deterministic firmware update timing for SPD programming stations |
| Standby Current | 1.6–4.0 μA - minimizes power draw during DIMM idle states without compromising wake responsiveness |
Pinout & Package
AT34C04-SS5M-B is packaged in an 8-lead JEDEC SOIC (SO-8) with standard pinout and lead-free, RoHS-compliant finish. Pin 1 is A0 (address/RSWP control), Pin 2 is A1, Pin 3 is A2, Pin 4 is GND, Pin 5 is VCC, Pin 6 is NC (no connect), Pin 7 is SCL, and Pin 8 is SDA.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Address input / RSWP enable | Configures slave address LSB; driven to 7–10 V to activate reversible software write protection commands |
| A1, A2 | Address inputs | Set remaining two LSBs of 7-bit I²C address (0x50–0x57); allow up to eight devices on same bus |
| GND | Power ground reference | Must be connected to system ground plane; serves as return path for all internal logic and I/O |
| VCC | Power supply input | Accepts 1.7–3.6 V; powers EEPROM core, interface logic, and high-voltage generation for RSWP |
| NC | No-connect terminal | Internally unconnected; may be tied to GND for mechanical stability or left floating |
| SCL | Serial clock input | Accepts I²C FM+ clocks up to 1 MHz; includes Schmitt trigger and noise filter for robust timing |
| SDA | Serial data bidirectional I/O | Open-drain output; requires external pull-up ≤8 kΩ; supports wire-OR with other I²C slaves |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC JC42.4 SPD Compliance | Fully satisfies DDR3/DDR4 module SPD requirements for standardized memory identification and timing parameter storage |
| Reversible Software Write Protection (RSWP) | Enables per-quadrant write lock/unlock via software command - no hardware fuses or permanent settings required |
| Legacy EE1002 Compatibility | Supports backward integration into existing 2-Kbit SPD systems using SPA/RPA addressing without firmware changes |
| Bus Timeout Protection | Resets interface and releases SDA if SCL held low >25 ms - prevents system hangs during I²C bus faults |
| Low-Voltage Operation | Functional down to 1.7 V - compatible with low-power DDR memory subsystems and battery-backed SPD configurations |
Applications
| DDR4 DIMM SPD Storage | DDR3 Server Memory Module |
|---|---|
Use Scenario: Storing JEDEC-defined SPD data (timing, voltage, size, thermal specs) on registered DDR4 UDIMMs/LRDIMMs during manufacturing and field updates. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed via I²C during BIOS POST to configure memory controller parameters. Use Value: Enables plug-and-play compatibility across vendor platforms while supporting in-field SPD reprogramming for firmware patches. | Use Scenario: Providing SPD data for enterprise-grade DDR3 RDIMMs used in rack-mount servers with ECC and thermal monitoring. IC Role / Device Role / Timing Role: SPD EEPROM interfacing with memory controller's SMBus host to deliver validated JEDEC timing profiles at boot. Use Value: Guarantees safe memory initialization by delivering accurate tRCD, tRP, and CAS latency values - preventing boot failures or instability. |
| Industrial Embedded Memory Modules | Automotive ADAS Memory Subsystems |
Use Scenario: Storing custom SPD extensions (vendor ID, revision, calibration offsets) in ruggedized DDR3 modules for industrial PLCs and HMIs operating at –40°C to +125°C. IC Role / Device Role / Timing Role: High-reliability SPD companion IC with 100-year data retention and 1M write cycles for infrequent but mission-critical updates. Use Value: Eliminates need for external backup power or supercapacitors during SPD writes - simplifies board design and reduces BOM cost. | Use Scenario: Supporting SPD functionality in automotive-grade DDR4 memory modules used in ADAS domain controllers requiring AEC-Q100 Grade 2 qualification. IC Role / Device Role / Timing Role: SPD EEPROM with Schmitt-trigger inputs and noise filtering to withstand EMI in vehicle cabin environments. Use Value: Ensures robust SPD communication despite high-noise CAN/FlexRay coexistence - avoids memory misconfiguration during cold starts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C04C-SSHM-T | 4-Kbit I²C EEPROM; lacks SPD-specific features (no RSWP, no SPA/RPA, not JC42.4 compliant) | General-purpose storage only - unsuitable for DDR SPD due to missing quadrant protection and legacy compatibility modes | Select only for non-SPD designs where JEDEC compliance and reversible write protection are unnecessary |
| STTS22HDTY | Temperature sensor with integrated 2-Kbit EEPROM; I²C interface but no SPD addressing or RSWP capability | Used for thermal monitoring + minimal config storage - cannot replace full SPD functionality or memory capacity | Consider only when combining temperature sensing and basic NVM in space-constrained modules; not a functional substitute |
Compared with AT24C04C-SSHM-T and STTS22HDTY, the AT34C04-SS5M-B uniquely delivers JEDEC JC42.4 compliance, quadrant-level RSWP, and SPA/RPA addressing - making it the only qualified choice for DDR3/DDR4 SPD implementations requiring field-programmable, secure, and standards-aligned memory configuration.
Availability
AT34C04-SS5M-B is available at Aetrix Electronics and suitable for DDR4 DIMM SPD storage, DDR3 server memory modules, industrial embedded memory modules, and automotive ADAS memory subsystems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for AT34C04-SS5M-B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full support for the AT34C04 family. Microchip is a global leader in microcontrollers, analog, FPGA, and memory solutions, serving industrial, automotive, and communications markets.
The AT34C04 product line was designed specifically for Serial Presence Detect in DRAM modules, delivering JEDEC-compliant, high-reliability EEPROM with advanced software protection for memory configuration data - targeting DDR3, DDR4, and future-generation DIMM applications.
FAQ
What is the primary application of the AT34C04-SS5M-B?
The AT34C04-SS5M-B is engineered for Serial Presence Detect (SPD) in DDR3 and DDR4 memory modules. It stores JEDEC-standardized module information - including size, speed, voltage, data width, and timing parameters - enabling automatic memory controller configuration during system boot. Its RSWP and SPA/RPA features ensure secure, field-updatable SPD data integrity.
Does the AT34C04-SS5M-B support I²C Fast-Mode Plus (1 MHz)?
Yes, the AT34C04-SS5M-B fully supports I²C Fast-Mode Plus up to 1 MHz, as confirmed in its datasheet (Atmel-8827G). This allows rapid SPD reads during system initialization while maintaining compatibility with standard I²C hosts. Bus timeout and Schmitt-trigger inputs ensure robust operation even at maximum speed.
How does the Reversible Software Write Protection (RSWP) work on the AT34C04-SS5M-B?
RSWP on the AT34C04-SS5M-B enables per-quadrant write lock/unlock via software commands using the A0 pin driven to 7–10 V. Each of the four 128-byte quadrants can be independently protected. Protection status is verified through dedicated read commands, and reversal requires a specific byte sequence - no hardware fuses or permanent settings are involved.
Is the AT34C04-SS5M-B compatible with legacy 2-Kbit SPD systems?
Yes, the AT34C04-SS5M-B maintains backward compatibility with JEDEC EE1002 (2-Kbit) SPD systems via its Set Page Address (SPA) and Read Page Address (RPA) commands. When SPA = 0, it emulates a 2-Kbit device occupying the lower 256 bytes - allowing integration into existing firmware without modification.
What package type is used for the AT34C04-SS5M-B?
The AT34C04-SS5M-B uses an 8-lead JEDEC SOIC (SO-8) package, designated as "SS" in the part number. It features gull-wing leads, Pb/Halide-free construction, and RoHS compliance. Pinout matches industry-standard SOIC-8 layout with A0–A2, GND, VCC, NC, SCL, and SDA terminals.
AT34C04-SS5M-B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 3.6V
- Operating Temperature:
- -20°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT34C04-SS5M-B FAQ
1.How can I place an order for AT34C04-SS5M-B through Aetrix?
Please submit a Request for Quotation (RFQ) for AT34C04-SS5M-B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT34C04-SS5M-B reliable?
The price and inventory of AT34C04-SS5M-B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT34C04-SS5M-B is usually 5 days.
3.What payment methods are accepted for AT34C04-SS5M-B?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT34C04-SS5M-B transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT34C04-SS5M-B?
AT34C04-SS5M-B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT34C04-SS5M-B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT34C04-SS5M-B?
For technical support, including AT34C04-SS5M-B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT34C04-SS5M-B requirements.
6.How does Aetrix verify that AT34C04-SS5M-B is sourced from the original manufacturer or authorized distributors?
All AT34C04-SS5M-B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT34C04-SS5M-B meets industry standards.
7.What is the process for return or replacement of AT34C04-SS5M-B?
All AT34C04-SS5M-B units undergo pre-shipment inspection (PSI). If there is an issue with AT34C04-SS5M-B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT34C04-SS5M-B part is unused and in its original packaging.
Return procedure for AT34C04-SS5M-B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT34C04-SS5M-B Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
