My Inquiry
My Account
Microchip Technology AT34C04-X5M-T
- Part No.:
- AT34C04-X5M-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT34C04-X5M-T.pdf
- Description:
- IC EEPROM 4KBIT I2C 1MHZ 8TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:5,536
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT34C04-X5M-T from Microchip Technology (formerly Atmel) is a 4-Kbit I²C-compatible Serial EEPROM designed for Serial Presence Detect (SPD) in DRAM modules. It provides 512 bytes × 8-bit memory organized into four 128-byte quadrants, supports 1.7V–3.6V operation, 1MHz Fast-Mode Plus I²C interface, and reversible software write protection - enabling secure storage of module timing, voltage, and configuration data in DDR3/DDR4 memory subsystems.
For engineers reviewing the AT34C04-X5M-T datasheet, AT34C04-X5M-T pinout, AT34C04-X5M-T application, or AT34C04-X5M-T equivalent, this device is selected for SPD-compliant DIMM design, legacy EE1002/EE1004-v system integration, quadrant-level data protection, and low-voltage embedded memory applications requiring 100-year data retention and 1M write-cycle endurance.
Technical Context
The AT34C04-X5M-T implements a dual-halves memory architecture with Set Page Address (SPA) and Read Page Address (RPA) commands to select upper or lower 256-byte sections - ensuring backward compatibility with JEDEC EE1002 2-Kbit SPD devices while supporting full 4-Kbit capacity. Its I²C FM+ interface operates up to 1 MHz with bus timeout (25–35 ms), Schmitt-triggered SDA/SCL inputs, and integrated spike suppression.
It features Reversible Software Write Protection (RSWP) per quadrant, enabled via A0 overvoltage (7–10 V) signaling, and supports partial page writes (16-byte pages), self-timed 5 ms max write cycles, and standby current as low as 1.6 µA at 1.7 V - all within JEDEC JC42.4-compliant SPD functionality.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 4096 bits (512 × 8), organized as four 128-byte quadrants for independent software write protection. |
| Supply Voltage | 1.7 V to 3.6 V - enables direct integration into low-voltage DDR3/DDR4 SPD rails without level shifting. |
| I²C Interface | Fast-Mode Plus (FM+) compatible up to 1 MHz - doubles bandwidth vs standard Fast-Mode, reducing SPD read latency. |
| Write Endurance | 1,000,000 cycles per quadrant - supports frequent SPD reprogramming during module calibration or firmware updates. |
| Data Retention | 100 years at +25°C - ensures long-term validity of SPD data across server/industrial memory lifecycle. |
| Write Cycle Time | ≤5 ms maximum - enables deterministic timing for SPD initialization sequences in BIOS/UEFI boot paths. |
| Standby Current | 1.6 µA at 1.7 V - minimizes power draw on memory module VDDQ rail during system sleep states. |
Pinout & Package
AT34C04-X5M-T is packaged in an 8-lead JEDEC SOIC (SOIC-8) with standard pinout and no internal connection on NC pin. All pins support 1.7–3.6 V logic levels, with A0 tolerant to 10 V for RSWP activation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Device address LSB / RSWP enable | Configures slave address bit 0; driven to 7–10 V to activate reversible quadrant write protection. |
| A1 | Device address bit 1 | Hardwired to VCC/GND to set unique I²C address (up to 8 devices on same bus). |
| A2 | Device address bit 2 | Hardwired to VCC/GND to complete 3-bit hardware address; enables multi-device SPD topology. |
| GND | Power ground reference | Must be connected to system ground plane; serves as return path for I²C pull-ups and internal logic. |
| VCC | Power supply input | Accepts 1.7–3.6 V; powers EEPROM core, interface, and high-voltage generation for RSWP. |
| NC | No-connect terminal | Not bonded internally; may be left floating or tied to GND for mechanical stability or EMI reduction. |
| SCL | Serial clock input | Open-drain input with Schmitt trigger; requires external pull-up; controls data sampling edges (rising latch/falling output). |
| SDA | Serial data bidirectional I/O | Open-drain bidirectional line with noise filtering; shared across I²C bus; must use ≤8 kΩ pull-up resistor. |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC JC42.4 (EE1004-v) SPD Compliance | Fully satisfies DDR3/DDR4 memory module SPD specification - guarantees BIOS/UEFI recognition and parameter auto-configuration. |
| Reversible Software Write Protection (RSWP) | Per-quadrant protection enabled/disabled via software command sequence - prevents accidental SPD corruption without permanent lockout. |
| Legacy EE1002 Compatibility | Protocol-identical to 2-Kbit SPD EEPROMs - allows drop-in replacement in existing DIMM designs without firmware changes. |
| Bus Timeout Function | Resets interface if SCL held low >25 ms - prevents system hang during I²C bus contention or master failure. |
| 16-byte Page Write Mode | Enables partial writes within 16-byte boundaries - optimizes SPD update efficiency and reduces write time vs byte-by-byte. |
Applications
| DRAM Module SPD Storage | Server Memory Configuration |
|---|---|
Use Scenario: Storing JEDEC-defined timing parameters, voltage settings, module size, and manufacturer ID on DDR4 UDIMMs. IC Role / Device Role / Timing Role: Dedicated SPD EEPROM providing nonvolatile configuration data to memory controller during power-on initialization. Use Value: Enables automatic memory training and stable XMP/AMP profile loading without manual BIOS setup. |
Use Scenario: Populating RDIMM/LRDIMM SPD data in enterprise servers where multiple memory channels require synchronized timing. IC Role / Device Role / Timing Role: System-level SPD agent storing channel-specific rank mapping and thermal derating tables. Use Value: Supports hot-plug DIMM detection and runtime SPD re-read during memory health monitoring. |
| Industrial Embedded Memory Calibration | Legacy DIMM Retrofit |
Use Scenario: Storing custom timing offsets and voltage margins for FPGA-based memory controllers in ruggedized edge computing platforms. IC Role / Device Role / Timing Role: Field-programmable SPD companion IC enabling post-manufacture memory tuning. Use Value: Allows firmware-driven SPD updates to compensate for temperature drift or aging effects. |
Use Scenario: Upgrading older DDR3 systems using EE1002-compliant 2-Kbit SPD EEPROMs to higher-density 4-Kbit capacity. IC Role / Device Role / Timing Role: Pin- and protocol-compatible SPD replacement preserving existing PCB layout and host driver stack. Use Value: Extends SPD data space for additional JEDEC extensions (e.g., thermal sensors, vendor-specific fields) without redesign. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C04D-SSHM-T | 4-Kbit I²C EEPROM with 1.7–5.5 V range; lacks SPA/RPA addressing and JEDEC EE1004-v SPD compliance. | General-purpose EEPROM use only - not validated for DDR SPD or JEDEC JC42.4 conformance testing. | Select when SPD compliance is unnecessary and wider voltage range or simpler addressing is preferred. |
| STTS222BTR | 2-Kbit JEDEC EE1004-v SPD EEPROM; supports only legacy 2-Kbit SPD map; no RSWP or quadrant protection. | Strictly limited to JEDEC-defined 256-byte SPD space - cannot store extended DDR4/DDR5 parameters. | Select for cost-sensitive DDR3 designs where full 4-Kbit capacity and field-upgradable protection are not required. |
Compared with AT24C04D-SSHM-T and STTS222BTR, the AT34C04-X5M-T uniquely delivers JEDEC JC42.4 SPD compliance, reversible quadrant-level write protection, and dual-halves memory addressing - making it the only option qualified for DDR4/DDR5 module SPD implementation with field-update security.
Availability
AT34C04-X5M-T is available at Aetrix Electronics and suitable for DRAM module manufacturing, server memory qualification, and industrial embedded memory calibration requiring stable component supply, long-lifecycle availability, and JEDEC-compliant SPD functionality.
Supply support for AT34C04-X5M-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains its serial EEPROM product lines with focus on reliability, longevity, and standards compliance for memory interface applications.
The AT34C04-X5M-T belongs to Microchip's SPD-optimized Serial EEPROM family, engineered specifically for JEDEC JC42.4-compliant DRAM module configuration and long-term data integrity in mission-critical memory subsystems.
FAQ
What is the operating voltage range of the AT34C04-X5M-T?
The AT34C04-X5M-T operates from 1.7 V to 3.6 V, making it compatible with DDR3L, DDR4, and LPDDR4 memory module VDDQ rails. This range ensures reliable read/write functionality across low-voltage memory subsystems without external level-shifting circuitry. The device's DC characteristics - including ICC1 (read current), ICC2 (write current), and ISB (standby current) - are fully specified across this entire voltage window per the Atmel-8827G datasheet.
Does the AT34C04-X5M-T support I²C Fast-Mode Plus (FM+)?
Yes, the AT34C04-X5M-T is explicitly I²C Fast-Mode Plus (FM+) compatible, supporting clock frequencies up to 1 MHz. Its AC characteristics table confirms tLOW/tHIGH timing compliance at 100 kHz, 400 kHz, and 1 MHz, with bus timeout (tOUT = 25–35 ms) and noise suppression (tI = 50 ns) built-in. This enables faster SPD reads during system boot compared to standard Fast-Mode devices, reducing memory initialization latency.
How does the Reversible Software Write Protection (RSWP) work on the AT34C04-X5M-T?
The AT34C04-X5M-T implements RSWP by allowing individual 128-byte quadrants to be write-protected via software command sequences. Protection is activated by driving the A0 pin to 7–10 V (VHV), then issuing the Set RSWP command (0x60–0x6F). Each quadrant's status can be verified using the Read RSWP command. Unlike permanent write protection, RSWP can be cleared using a dedicated Clear RSWP command - restoring full programmability without hardware intervention.
Is the AT34C04-X5M-T pin-compatible with legacy 2-Kbit SPD EEPROMs?
The AT34C04-X5M-T uses the same 8-pin SOIC package and identical pinout (A0–A2, SDA, SCL, VCC, GND, NC) as JEDEC EE1002-compliant 2-Kbit SPD EEPROMs. Its protocol-level compatibility - including device address structure, ACK/NACK behavior, and control byte formats - enables drop-in replacement in existing DIMM designs. However, full 4-Kbit utilization requires host firmware support for Set Page Address (SPA) commands to access upper quadrants.
What is the memory organization of the AT34C04-X5M-T?
The AT34C04-X5M-T contains 512 bytes of EEPROM organized as four 128-byte quadrants (Quadrant 0–3), grouped into two 256-byte halves. Access to each half is controlled via Set Page Address (SPA) and Read Page Address (RPA) commands. This dual-halves architecture preserves backward compatibility with 2-Kbit SPD layouts while enabling expanded data storage for DDR4/DDR5 extensions such as thermal sensor calibration or vendor-specific fields.
AT34C04-X5M-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 3.6V
- Operating Temperature:
- -20°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
AT34C04-X5M-T FAQ
1.How can I place an order for AT34C04-X5M-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT34C04-X5M-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT34C04-X5M-T reliable?
The price and inventory of AT34C04-X5M-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT34C04-X5M-T is usually 5 days.
3.What payment methods are accepted for AT34C04-X5M-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT34C04-X5M-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT34C04-X5M-T?
AT34C04-X5M-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT34C04-X5M-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT34C04-X5M-T?
For technical support, including AT34C04-X5M-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT34C04-X5M-T requirements.
6.How does Aetrix verify that AT34C04-X5M-T is sourced from the original manufacturer or authorized distributors?
All AT34C04-X5M-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT34C04-X5M-T meets industry standards.
7.What is the process for return or replacement of AT34C04-X5M-T?
All AT34C04-X5M-T units undergo pre-shipment inspection (PSI). If there is an issue with AT34C04-X5M-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT34C04-X5M-T part is unused and in its original packaging.
Return procedure for AT34C04-X5M-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT34C04-X5M-T Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
