Renesas AT45DB161D-SU
- Part No.:
- AT45DB161D-SU
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
AT45DB161D-SU.pdf
- Description:
- IC FLASH 16MBIT SPI 66MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,546
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Product details
Overview
AT45DB161D-SU from Adesto Technologies (now part of Dialog Semiconductor) is a 16-Mbit serial DataFlash memory IC with RapidS™ SPI interface, supporting up to 66 MHz clock frequency and dual 512-/528-byte SRAM buffers for concurrent read/write operations. It features page, block, sector, and chip erase modes, hardware/software write protection, and 100,000 program/erase cycles per page - ideal for firmware storage and code shadowing in embedded systems.
For engineers reviewing the AT45DB161D-SU datasheet, AT45DB161D-SU pinout, AT45DB161D-SU application, or AT45DB161D-SU equivalent, key selection considerations include its 2.5V–3.6V supply range, flexible page size configuration (512/528 bytes), continuous array read capability, RDY/BUSY signaling, and industrial temperature operation (–40°C to +85°C).
Technical Context
The AT45DB161D-SU implements a sequential-access Flash architecture with two independent 512-/528-byte SRAM buffers enabling simultaneous data reception and Flash reprogramming. Its RapidS serial interface supports SPI Modes 0 and 3, with command-driven operations including buffer-to-page programming (with or without built-in erase), and multi-granularity erase (page/4KB block/128KB sector/16Mbit chip).
Memory organization comprises 4,096 pages × 512 or 528 bytes, plus a 128-byte security register (64-byte user-programmable + 64-byte unique device ID). All erase and program cycles are self-timed, with status indicated via RDY/BUSY open-drain output and internal status register.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 16 Mbit (2,097,152 bytes), organized as 4,096 pages of 512 or 528 bytes |
| Interface | RapidS™ serial SPI-compatible (Modes 0 & 3), up to 66 MHz clock - enables high-speed streaming without address bus overhead |
| Supply Voltage | 2.5V–3.6V or 2.7V–3.6V single supply - compatible with modern low-voltage microcontrollers and eliminates need for charge pumps |
| Power Consumption | 7 mA typical active read current; 25 µA standby; 15 µA deep power-down - supports battery-powered and energy-sensitive designs |
| Erase Endurance | ≥100,000 program/erase cycles per page - ensures long-term reliability in firmware update and logging applications |
| Data Retention | 20 years at +85°C - validated for industrial lifecycle requirements without refresh |
| Operating Temperature | –40°C to +85°C industrial grade - suitable for automotive body electronics, industrial HMIs, and outdoor IoT nodes |
Pinout & Package
AT45DB161D-SU is supplied in an 8-pin SOIC package (300 mil width) with standard lead finish and RoHS-compliant green packaging.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable; falling edge initiates command sequence; high-impedance SO when deasserted |
| SCK | Serial Clock | Input clock; SI data latched on rising edge; SO data clocked out on falling edge |
| SI | Serial Input | Command, address, and data input; MSB-first protocol; synchronous to SCK rising edge |
| SO | Serial Output | Data output during read operations; tri-stated when CS is high |
| WP | Write Protect | Hardware-level sector lock override; low = blocks program/erase regardless of software protection state |
| RESET | Reset | Active-low hard reset; terminates ongoing operation and returns state machine to idle |
| RDY/BUSY | Ready/Busy Indicator | Open-drain output pulled high externally; driven low during self-timed operations (program/erase/buffer transfer) |
| VCC / GND | Power Supply / Ground | Single 2.5–3.6V supply; decoupling required near VCC pin for noise immunity in high-speed SPI |
Key Features
| Feature | Design Value |
|---|---|
| Dual SRAM Buffers | Two independent 512-/528-byte buffers allow background Flash programming while receiving new data - eliminates write latency bottlenecks in streaming applications |
| Continuous Array Read | Legacy (E8H), High-Freq (0BH), and Low-Freq (03H) read modes support seamless code shadowing across page boundaries with no wrap delay |
| Flexible Erase Granularity | Page (512B), Block (4KB), Sector (128KB), and Chip (16Mbit) erase options enable precise wear leveling and partial firmware updates |
| Security Register | 128-byte dedicated register with 64-byte user space + 64-byte factory-unique ID - supports secure boot key storage and device authentication |
| Hardware Write Protection | WP pin provides unconditional sector lock override, independent of software commands - critical for fail-safe firmware integrity |
Applications
| Firmware Storage | Code Shadowing |
|---|---|
|
Use Scenario: Storing bootloader and application firmware in resource-constrained microcontroller systems where external Flash replaces internal ROM limitations. IC Role / Device Role / Timing Role: Nonvolatile program memory accessed via SPI; supports in-system reprogramming without high-voltage programming signals. Use Value: Enables field-upgradable firmware with 100K-cycle endurance and 20-year retention - reduces BOM cost vs. parallel NOR Flash. |
Use Scenario: Copying executable code from Flash to RAM at system startup for faster execution in MCUs with limited internal Flash. IC Role / Device Role / Timing Role: Sequential-access memory with continuous read mode (E8H/0BH) delivering uninterrupted 66 MHz data stream across page boundaries. Use Value: Eliminates page-boundary stalls during shadowing, improving boot time predictability and reducing CPU wait states. |
| Data Logging | Secure Configuration Storage |
|
Use Scenario: Recording sensor readings or event logs in industrial controllers where power loss resilience and long-term data integrity are essential. IC Role / Device Role / Timing Role: Page-erasable nonvolatile storage with dual buffers enabling concurrent log buffering and Flash commit. Use Value: Prevents data loss during unexpected power failure by allowing atomic page writes and minimizing erase overhead per log entry. |
Use Scenario: Storing calibration parameters, cryptographic keys, and device-specific credentials in medical or payment terminals. IC Role / Device Role / Timing Role: Security register with factory-unique 64-byte ID and user-programmable 64-byte space - isolated from main memory array. Use Value: Provides tamper-resistant storage for sensitive data without requiring external secure elements or additional crypto ICs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial Flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT45DB161E-SU | Direct successor with enhanced reliability; identical pinout, timing, and command set; supports same voltage ranges and page sizes | Recommended for new designs per manufacturer notice; offers improved ESD tolerance and extended lifecycle support | Select AT45DB161E-SU for new projects; AT45DB161D-SU remains viable for legacy design continuity and obsolescence mitigation |
| W25Q16JVSSIQ | 16-Mbit Quad SPI Flash; supports 4-line I/O (QPI), higher max clock (104 MHz), but lacks dual SRAM buffers and continuous read wrap | Better throughput in QPI mode, but requires more complex driver support and lacks seamless code shadowing capability | Choose W25Q16JVSSIQ when bandwidth >66 MHz is needed and dual-buffer streaming is not required |
Compared with AT45DB161E-SU, the AT45DB161D-SU offers identical functionality but lacks updated process enhancements and long-term availability assurance; versus W25Q16JVSSIQ, it trades raw speed for deterministic continuous-read behavior and integrated buffer management - critical for real-time code shadowing and streaming data logging.
Availability
AT45DB161D-SU is available at Aetrix Electronics and suitable for firmware storage, code shadowing, data logging, and secure configuration storage requiring stable component supply across industrial, medical, and embedded control applications.
Supply support for AT45DB161D-SU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Adesto Technologies, acquired by Dialog Semiconductor in 2020, specialized in low-power, high-reliability serial Flash and nonvolatile memory solutions for embedded systems.
The AT45DB161D belongs to the DataFlash® family, designed specifically for applications demanding seamless sequential access, concurrent buffer operations, and robust data integrity in space- and power-constrained environments.
FAQ
What is the maximum SPI clock frequency supported by the AT45DB161D-SU?
The AT45DB161D-SU supports up to 66 MHz for Continuous Array Read (0BH/E8H commands) and Main Memory Page Read (D2H), as specified by fCAR1 and fSCK parameters. This enables high-throughput streaming for code shadowing and firmware loading without address bus overhead or parallel interface complexity.
Does the AT45DB161D-SU require high-voltage programming?
No, the AT45DB161D-SU operates entirely from its 2.5V–3.6V supply rail for both read and program/erase operations. It contains no charge pump or high-voltage generator, eliminating external voltage boost circuitry and simplifying system design compared to conventional Flash devices.
How does the dual-buffer architecture of the AT45DB161D-SU improve system performance?
The AT45DB161D-SU's two independent 512-/528-byte SRAM buffers allow simultaneous data reception into one buffer while the other buffer transfers content to Flash memory. This overlap eliminates idle time during page programming, enabling true continuous data streaming in logging and firmware update applications.
Can the AT45DB161D-SU be used for EEPROM emulation?
Yes, the AT45DB161D-SU supports EEPROM emulation via a three-step read-modify-write sequence using its buffers. Its page-erasable architecture and 100,000-cycle endurance per page make it suitable for byte-alterable storage in applications like parameter retention and calibration data logging.
What is the purpose of the RDY/BUSY pin on the AT45DB161D-SU?
The RDY/BUSY pin on the AT45DB161D-SU is an open-drain output that goes low during all self-timed operations - including program, erase, and buffer-to-memory transfers - signaling the host processor to pause command issuance until completion. This eliminates polling overhead and ensures reliable timing-critical operation.
AT45DB161D-SU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 16Mbit
- Memory Organization:
- 528 Bytes x 4096 pages
- Memory Interface:
- SPI
- Clock Frequency:
- 66 MHz
- Write Cycle Time - Word, Page:
- 6ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT45DB161D-SU FAQ
1.How can I place an order for AT45DB161D-SU through Aetrix?
Please submit a Request for Quotation (RFQ) for AT45DB161D-SU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT45DB161D-SU reliable?
The price and inventory of AT45DB161D-SU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT45DB161D-SU is usually 5 days.
3.What payment methods are accepted for AT45DB161D-SU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT45DB161D-SU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT45DB161D-SU?
AT45DB161D-SU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT45DB161D-SU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT45DB161D-SU?
For technical support, including AT45DB161D-SU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT45DB161D-SU requirements.
6.How does Aetrix verify that AT45DB161D-SU is sourced from the original manufacturer or authorized distributors?
All AT45DB161D-SU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT45DB161D-SU meets industry standards.
7.What is the process for return or replacement of AT45DB161D-SU?
All AT45DB161D-SU units undergo pre-shipment inspection (PSI). If there is an issue with AT45DB161D-SU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT45DB161D-SU part is unused and in its original packaging.
Return procedure for AT45DB161D-SU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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