Microchip Technology AT49F002-90JC
- Part No.:
- AT49F002-90JC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT49F002-90JC.pdf
- Description:
- IC FLASH 2MBIT PARALLEL 32PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:4,423
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT49F002-90JC from Atmel is a 5V-only, 2 Mbit (256K × 8) in-system reprogrammable Flash memory IC with 90 ns read access time, 10 µs/byte typical programming time, and sector-based architecture including a 16K-byte boot block with programmable lockout. It operates across commercial temperature range (0°C to 70°C) and is used for firmware storage and boot code retention in embedded microcontroller systems.
For engineers reviewing the AT49F002-90JC datasheet, AT49F002-90JC pinout, AT49F002-90JC application, or AT49F002-90JC equivalent, key selection considerations include its PLCC-32 package, 5V single-supply operation, hardware data protection features, DATA polling/Toggle Bit erase-program status detection, and boot block write-protection capability.
Technical Context
The AT49F002-90JC implements a command-register-based architecture requiring six-byte sequences for chip/sector erase and boot lockout enable. Its internal program control logic manages timing without external clocks, supporting software-controlled erasure of parameter blocks (2 × 8K bytes) and main memory blocks (96K + 128K bytes).
It uses standard EPROM-compatible control signals (CE/OE/WE) for read access and supports hardware reset-driven boot block override at 12 V. The device integrates VCC sense, noise filtering on WE/CE, and TTL/CMOS-level input thresholds to prevent inadvertent writes during power transitions or noise events.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 2 Mbit (262,144 × 8), organized as 256K words × 8 bits - sufficient for full boot firmware images in 8-bit/16-bit MCU platforms. |
| Read Access Time | 90 ns max - meets timing requirements for 11 MHz bus interfaces in legacy industrial controllers. |
| Byte Programming Time | 10 µs typical - enables rapid field updates of configuration parameters without system downtime. |
| Erase Cycle Time | 10 seconds max - allows full-chip or sector erase within predictable maintenance windows. |
| End-of-Operation Detection | DATA polling (I/O7 complement) and Toggle Bit (I/O6 toggling) - eliminates need for fixed delay timers in host firmware. |
| Power Dissipation | 50 mA active / 100 µA CMOS standby - supports low-power modes in battery-backed or energy-conscious designs. |
| Endurance | 10,000 write/erase cycles - validated for long-term use in firmware update-capable instrumentation and telecom modules. |
Pinout & Package
AT49F002-90JC is housed in a 32-lead Plastic J-leaded Chip Carrier (PLCC) package, compliant with JEDEC MS-016 AE. Pin 1 is marked by index notch; pin 16 is GND, pin 32 is VCC. Pin 1 (RESET) functions as DC (no-connect) for AT49F002N(T) variants but is active on AT49F002(T); per ordering code suffix and documentation, AT49F002-90JC corresponds to the base AT49F002(N) variant where RESET is functional.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A17 | Address Inputs | 18-bit address bus supporting full 256K-word addressing; A0–A14 used for software ID mode. |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for valid read access. |
| OE | Output Enable | Active-low output gate; controls data bus tristate to prevent contention during shared-bus operation. |
| WE | Write Enable | Active-low write strobe; latches address/data on falling/rising edges per command sequence timing. |
| RESET | Reset Input | Active-low reset; halts ongoing operations and forces outputs to high-Z; 12 V override enables boot block reprogramming. |
| I/O0–I/O7 | Data I/O Bus | Bidirectional 8-bit data path; I/O0 indicates boot lockout status in ID mode; I/O6 = Toggle Bit; I/O7 = DATA polling indicator. |
| GND / VCC | Power Supply | Single 5V ±10% supply; no VPP required - simplifies PCB power design and eliminates high-voltage generation circuitry. |
Key Features
| Feature | Design Value |
|---|---|
| Sector Architecture with Boot Block Lockout | Enables permanent storage of secure boot code (00000H–03FFFH) while allowing field updates to application firmware in main memory blocks. |
| Hardware Data Protection | VCC sense (<3.8 V inhibits programming), noise filtering (<15 ns pulses ignored), and control-line interlock (OE low/CE high/WE high prevents writes) ensure robustness in noisy industrial environments. |
| Two-Method Operation Status Detection | Simultaneous support for DATA polling (I/O7 inversion) and Toggle Bit (I/O6 oscillation) gives host firmware flexibility in monitoring erase/program completion without fixed delays. |
| 5V-Only Reprogrammability | Eliminates need for 12 V programming supplies or external voltage translators - reduces BOM cost and layout complexity in embedded systems. |
| Standard Microprocessor Interface | Uses CE/OE/WE control scheme identical to EPROMs - enables drop-in replacement in legacy designs without modifying bus interface logic or timing constraints. |
Applications
| Industrial PLC Firmware Storage | Legacy Embedded Controller Boot Memory |
|---|---|
Use Scenario: Storing firmware and configuration data in programmable logic controllers subject to frequent field updates and long service life. IC Role / Device Role / Timing Role: Nonvolatile boot memory providing fast 90 ns read access during cold start and reliable byte-programming for parameter tuning. Use Value: Sector erase capability isolates parameter updates from main firmware, reducing risk of bricking the controller during partial reprogramming. | Use Scenario: Replacing UV-erasable EPROMs in aging 8-bit microcontroller-based instrumentation where board space and supply count are constrained. IC Role / Device Role / Timing Role: Direct EPROM drop-in replacement with identical pinout and timing, enabling upgrade without PCB redesign. Use Value: Eliminates need for UV erasers and socket programming; in-system reprogrammability cuts maintenance time and logistics overhead. |
| Secure Boot Code Retention | Telecom Line Card Configuration Storage |
Use Scenario: Protecting immutable bootloader code in network edge devices that require verified startup sequences before loading application firmware. IC Role / Device Role / Timing Role: Boot block (00000H–03FFFH) with hardware-enforced lockout prevents accidental or malicious overwrite of critical startup routines. Use Value: 12 V RESET override allows authorized recovery of corrupted boot code - balancing security with serviceability. | Use Scenario: Holding calibration data, MAC addresses, and feature-enable flags in modular telecom line cards deployed across diverse environmental conditions. IC Role / Device Role / Timing Role: Low-power (100 µA standby) Flash memory retaining settings across power cycles and thermal stress. Use Value: 10,000-cycle endurance ensures reliable operation over 10+ years of field service with periodic configuration updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AM29LV002BT-90EC | 48-pin TSOP package; 3.0–3.6 V core supply with 5 V I/O tolerance; 90 ns read; no RESET pin; boot block at top address (3C000H–3FFFFH) | Requires level-shifting for 5 V-only systems; lacks 12 V boot override; different sector map invalidates direct firmware porting | Select only if migrating to 3.3 V system architecture and redesigning power delivery and signal interfacing. |
| SST39VF020-90-4C-NHE | 32-pin TSOP; 3.0–3.6 V operation; 90 ns read; 512-byte page programming; no hardware RESET pin; boot block at bottom (00000H–03FFFH) | Not 5 V compatible; requires external 3.3 V regulator; lacks 12 V override; different command set increases firmware porting effort | Choose only when upgrading to modern low-voltage platforms and accepting full firmware adaptation effort. |
Compared with AM29LV002BT-90EC and SST39VF020-90-4C-NHE, the AT49F002-90JC uniquely supports true 5 V-only operation with functional RESET pin and 12 V boot override - making it the only option for maintaining legacy 5 V designs requiring field-recoverable boot integrity.
Availability
AT49F002-90JC is available at Aetrix Electronics and suitable for industrial PLC firmware storage, legacy embedded controller boot memory, secure boot code retention, and telecom line card configuration storage requiring stable component supply and long-term obsolescence management.
Supply support for AT49F002-90JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication solutions.
The AT49F002 product line was designed for 5 V embedded systems requiring in-system reprogrammable Flash memory with robust data integrity, sector-level erase granularity, and hardware-protected boot code storage.
FAQ
What is the operating temperature range for the AT49F002-90JC?
The AT49F002-90JC is rated for commercial temperature operation from 0°C to 70°C, as indicated by the "C" suffix in the ordering code. This makes it suitable for indoor industrial equipment, office automation devices, and consumer electronics where ambient thermal conditions remain within this envelope. The device's DC and AC characteristics-including 90 ns read access and 100 µA standby current-are guaranteed across this full range.
Does the AT49F002-90JC require a high-voltage programming supply?
No, the AT49F002-90JC operates with a single 5 V ±10% supply for both read and reprogramming functions. It does not require VPP or any external high-voltage source. All command sequences-including byte programming, sector erase, and boot lockout-execute using standard 5 V logic levels, simplifying power design and eliminating voltage translation circuitry in host systems.
How is boot block protection enabled and overridden on the AT49F002-90JC?
Boot block protection on the AT49F002-90JC is enabled via a six-cycle command sequence (AAh/55h/80h/AAh/55h/40h) written to address 5555h. Once enabled, the 16K-byte boot block (00000H–03FFFH) becomes permanently write-protected at ≤5.5 V. Override is achieved by applying 12.0 V ±0.5 V to the RESET pin, which temporarily disables lockout for chip/sector erase or byte programming - a feature confirmed for the AT49F002(N) variant used in AT49F002-90JC.
What package type is used for the AT49F002-90JC?
The AT49F002-90JC uses a 32-lead Plastic J-leaded Chip Carrier (PLCC) package, designated as 32J per Atmel's ordering information. It measures 1.67″ × 1.64″ (42.4 mm × 41.7 mm) with J-shaped leads, and features an index notch for pin 1 identification. This surface-mount package offers mechanical robustness and thermal performance suitable for reflow-soldered industrial assemblies.
Can the AT49F002-90JC be used as a direct replacement for standard EPROMs like the 27C256?
Yes, the AT49F002-90JC provides pin-for-pin and functionally compatible replacement for 27C256 EPROMs in 32-pin DIP or PLCC footprints, with identical CE/OE/WE control signaling and read timing. Unlike EPROMs, it supports in-system reprogramming without UV erasure or socket removal. However, firmware must implement Atmel's command sequences for erase/program - no hardware changes are needed, but software adaptation is required for non-read operations.
AT49F002-90JC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 2Mbit
- Memory Organization:
- 256K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 50µs
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT49F002-90JC FAQ
1.How can I place an order for AT49F002-90JC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT49F002-90JC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT49F002-90JC reliable?
The price and inventory of AT49F002-90JC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT49F002-90JC is usually 5 days.
3.What payment methods are accepted for AT49F002-90JC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT49F002-90JC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT49F002-90JC?
AT49F002-90JC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT49F002-90JC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT49F002-90JC?
For technical support, including AT49F002-90JC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT49F002-90JC requirements.
6.How does Aetrix verify that AT49F002-90JC is sourced from the original manufacturer or authorized distributors?
All AT49F002-90JC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT49F002-90JC meets industry standards.
7.What is the process for return or replacement of AT49F002-90JC?
All AT49F002-90JC units undergo pre-shipment inspection (PSI). If there is an issue with AT49F002-90JC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT49F002-90JC part is unused and in its original packaging.
Return procedure for AT49F002-90JC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT49F002-90JC Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

