Microchip Technology AT49LH004-33JC
- Part No.:
- AT49LH004-33JC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT49LH004-33JC.pdf
- Description:
- IC FLASH 4MBIT PAR 33MHZ 32PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:4,654
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Product details
Overview
AT49LH004-33JC from Microchip Technology is a 4-Mbit Firmware Hub (FWH) and Low-Pin Count (LPC) Flash memory IC designed for BIOS storage in Intel 8xx/E7xxx/E8xxx and non-Intel chipset platforms. It supports dual-interface operation (FWH/LPC and A/A Mux), features 32-Kbyte top boot sector + flexible 8/16/64-Kbyte sectoring, operates at 3.0–3.6 V, and uses a 33 MHz PCI clock for FWH/LPC timing.
For engineers reviewing the AT49LH004-33JC datasheet, AT49LH004-33JC pinout, AT49LH004-33JC application, or AT49LH004-33JC equivalent, key selection considerations include LPC/FWH interface auto-detection, hardware write protection via TBL/WP pins, sector locking register support, 32-lead PLCC package compatibility, and single-voltage 3.3 V system integration.
Technical Context
The AT49LH004-33JC implements a dual-mode interface architecture controlled by the IC pin: low enables FWH/LPC mode (5-signal, 33 MHz PCI-synchronous, byte-level transfers); high enables A/A Mux mode (11-pin multiplexed address + 8-bit data, R/C-latched addressing). Sector erase configuration is determined by command selection - one command yields 11 non-uniform sectors (32K+2×8K+16K+7×64K), another yields eight uniform 64-Kbyte sectors.
Internal Command User Interface (CUI) manages command sequencing across both interfaces. The device decodes only A23–A0 of the 28-bit FWH address space (ignoring A27–A24 and A21–A19), with A22 selecting between memory array (A22=1) and register space (A22=0). Status reporting uses RDY/BSY (pin 23 in PLCC) reflecting Status Register bit 7.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 4 Mbit (512 Kbytes) total storage capacity |
| Interface Modes | FWH/LPC (5-signal, 33 MHz PCI clock) and A/A Mux (11-pin address + 8-bit data) |
| Sector Architecture | Configurable: 11-sector (32K top boot + 2×8K + 16K + 7×64K) or 8×64K uniform erase |
| Supply Voltage | 3.0 V to 3.6 V - single supply for read, program, and erase operations |
| Hardware Protection | Dedicated TBL pin (top boot lock) and WP pin (all other sectors) |
| Package Type | 32-lead Plastic Leaded Chip Carrier (PLCC), lead-free and RoHS-compliant |
| Timing Model | Fixed program/erase times - no system calibration required across endurance cycles |
Pinout & Package
AT49LH004-33JC is packaged in a 32-lead PLCC (Plastic Leaded Chip Carrier) with 0.050-inch lead pitch, compliant with JEDEC MS-026AC. Pin functions are dual-role: FWH/LPC interface used in-system; A/A Mux interface used during manufacturing programming. Interface selection is controlled by the IC pin (pin 11).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IC (Pin 11) | Interface Configuration Control | Low = FWH/LPC mode active; high = A/A Mux mode active; internal pull-down ensures default FWH/LPC if unconnected |
| FWH4/LFRAME (Pin 12) | LPC Frame / Write Enable | Indicates start/abort of FWH/LPC cycle; serves as WE in A/A Mux mode |
| TBL (Pin 15) | Top Boot Sector Lock | Hardware write/erase protection for top 32-Kbyte boot sector (LPC) or top 64-Kbyte region (FWH) |
| WP (Pin 16) | Write Protect | Hardware lock for all non-top-boot sectors; independent of sector locking registers |
| ID[3:0] (Pins 17–20) | Device Identification Inputs | Strap 4-bit ID for multi-device bus selection; boot device must be 0000; internally pulled down |
| GPI[4:0] (Pins 1, 2, 21, 22, 30) | General-Purpose Inputs | Readable via GPI register; provide board-level flexibility for status sensing or configuration detection |
| RST (Pin 29) | Interface Reset | Resets internal automation, inhibits writes, places FWH/LAD[3:0] in high-Z; defaults to read array mode on exit |
Key Features
| Feature | Design Value |
|---|---|
| Auto-detect FWH vs. LPC cycles | Enables seamless use with Intel chipsets (as FWH) and non-Intel platforms (as LPC Flash) without firmware reconfiguration |
| Two configurable erase architectures | Optimizes BIOS code layout: 11-sector mode minimizes wasted space for legacy module alignment; 8×64K mode simplifies uniform firmware updates |
| Dual-interface support (FWH/LPC + A/A Mux) | Separates in-system operation (FWH/LPC) from high-speed manufacturing programming (A/A Mux), reducing test time and tooling cost |
| Hardware + register-based sector protection | TBL/WP pins provide immediate physical lock; sector locking registers allow dynamic, software-controlled per-sector read/write enable/disable |
| PCI-compliant FWH/LPC buffers | Ensures signal integrity and timing compliance when interfacing directly with ICH or south bridge controllers on 33 MHz PCI clock domain |
Applications
| Intel Desktop Motherboard BIOS | Embedded Industrial Controller Firmware |
|---|---|
Use Scenario: Storing and updating core BIOS code on Intel 8xx-series chipset-based desktop motherboards with ICH south bridge. IC Role / Device Role / Timing Role: Firmware Hub (FWH) providing secure, authenticated boot code storage with hardware-protected top boot sector. Use Value: Enables reliable cold boot and recovery via TBL-locked 32-Kbyte boot sector while supporting full-field firmware updates to remaining sectors using FWH memory write cycles. | Use Scenario: Hosting firmware images for fanless industrial controllers requiring long-term BIOS stability and field-upgradable feature sets. IC Role / Device Role / Timing Role: LPC Flash memory operating in non-Intel chipset environments, accessed via standard LPC bus protocol. Use Value: Delivers deterministic 33 MHz–synchronized read/write timing and uniform 64-Kbyte sector erase for predictable firmware update windows in real-time control systems. |
| Notebook Platform UEFI Firmware | Legacy PC BIOS Recovery Module |
Use Scenario: Storing UEFI firmware volumes on compact notebook platforms where PCB space limits component count and voltage options. IC Role / Device Role / Timing Role: Single-supply 3.3 V Flash memory with A/A Mux interface for factory programming and FWH/LPC for runtime access. Use Value: Eliminates need for dual-voltage programming equipment; supports in-system firmware patching via FWH interface without board rework. | Use Scenario: Implementing a dedicated recovery partition in legacy PC BIOS that remains immune to accidental corruption during main BIOS updates. IC Role / Device Role / Timing Role: Top-boot protected Flash sector acting as immutable fallback image storage. Use Value: Guarantees recovery capability via hardware-enforced TBL pin lock - no software vulnerability can overwrite the top 32-Kbyte boot sector. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar firmware flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W29GL032C | 32-Mbit density, supports SPI + Parallel interfaces; lacks FWH/LPC compliance and TBL/WP hardware pins | Designed for general-purpose embedded firmware, not Intel chipset BIOS integration | Choose only if migrating to SPI-based platform or requiring higher density without FWH protocol dependency |
| Macronix MX29LV320ET | 32-Mbit, 3.0–3.6 V, supports Common Flash Interface (CFI); no IC pin or dual-interface logic | Targeted at legacy parallel NOR applications; requires external address/data bus and separate OE/WE controls | Select when replacing older parallel Flash in non-LPC designs where CFI command set and JEDEC-standard timing are required |
Compared with W29GL032C and MX29LV320ET, the AT49LH004-33JC uniquely delivers Intel LPC/FWH protocol compliance, hardware boot-sector protection, and dual-interface configurability - making it irreplaceable in certified Intel-platform BIOS implementations despite its 4-Mbit capacity limitation.
Availability
AT49LH004-33JC is available at Aetrix Electronics and suitable for Intel chipset motherboard BIOS, embedded controller firmware, notebook UEFI storage, legacy PC recovery modules, and industrial system boot code applications requiring stable component supply and long-lifecycle support.
Supply support for AT49LH004-33JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, Flash memory, and security solutions for industrial, automotive, and computing markets.
The AT49LH004-33JC belongs to Microchip's legacy Firmware Hub and LPC Flash memory product line, engineered specifically to meet Intel's BIOS firmware storage requirements with hardware-level security, dual-interface flexibility, and 3.3 V system compatibility.
FAQ
What interface protocols does the AT49LH004-33JC support?
The AT49LH004-33JC supports two distinct interface protocols: the Intel Firmware Hub (FWH) and Low-Pin Count (LPC) interface for in-system operation, and the Address/Address Multiplexed (A/A Mux) interface for manufacturing programming. Interface selection is controlled by the IC pin state. The FWH/LPC interface uses a 5-signal, 33 MHz PCI-synchronous protocol with FWH/LAD[3:0] and FWH4/LFRAME; the A/A Mux interface uses 11-pin multiplexed address lines and 8-bit bidirectional data. Both are fully implemented in the AT49LH004-33JC.
How does hardware write protection work on the AT49LH004-33JC?
The AT49LH004-33JC provides two dedicated hardware write protect pins: TBL (pin 15) locks the top 32-Kbyte boot sector in LPC mode or top 64-Kbyte region in FWH mode, and WP (pin 16) protects all remaining sectors. When asserted low, these pins override software-based sector locking registers and physically inhibit program/erase operations. The AT49LH004-33JC maintains this protection even during power transitions, ensuring boot integrity without firmware intervention.
What sector erase configurations are available for the AT49LH004-33JC?
The AT49LH004-33JC offers two configurable sector erase architectures selectable via command: one yields 11 sectors (32-Kbyte top boot + two 8-Kbyte + one 16-Kbyte + seven 64-Kbyte), optimized for legacy BIOS module alignment; the other yields eight uniform 64-Kbyte sectors for simplified firmware updates. Both configurations are supported natively by the AT49LH004-33JC and require no hardware changes - only different erase command sequences.
Is the AT49LH004-33JC compatible with modern Intel chipsets?
The AT49LH004-33JC complies with Intel's LPC Interface Specification Revision 1.1 and is explicitly qualified for use with Intel 8xx, E7xxx, and E8xxx series chipsets as a Firmware Hub device. While newer platforms have migrated to SPI-based firmware storage, the AT49LH004-33JC remains functionally compatible with legacy and extended-life Intel platforms that retain LPC bus support. Its FWH protocol implementation is fully validated per specification in the AT49LH004-33JC datasheet.
What is the purpose of the GPI pins on the AT49LH004-33JC?
The AT49LH004-33JC includes five General-Purpose Input (GPI) pins (GPI0–GPI4) that provide system-level flexibility: they can be read via the GPI register using the FWH/LPC interface to detect board revisions, jumper settings, or hardware configuration states. These pins serve as strappable inputs during power-up and remain readable throughout operation, enabling dynamic firmware behavior adaptation without additional GPIO controllers. All five GPI pins are implemented and functional in the AT49LH004-33JC.
AT49LH004-33JC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 4Mbit
- Memory Organization:
- 512K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- 33 MHz
- Write Cycle Time - Word, Page:
- 50µs
- Access Time:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- 0°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT49LH004-33JC FAQ
1.How can I place an order for AT49LH004-33JC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT49LH004-33JC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT49LH004-33JC reliable?
The price and inventory of AT49LH004-33JC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT49LH004-33JC is usually 5 days.
3.What payment methods are accepted for AT49LH004-33JC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT49LH004-33JC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT49LH004-33JC?
AT49LH004-33JC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT49LH004-33JC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT49LH004-33JC?
For technical support, including AT49LH004-33JC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT49LH004-33JC requirements.
6.How does Aetrix verify that AT49LH004-33JC is sourced from the original manufacturer or authorized distributors?
All AT49LH004-33JC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT49LH004-33JC meets industry standards.
7.What is the process for return or replacement of AT49LH004-33JC?
All AT49LH004-33JC units undergo pre-shipment inspection (PSI). If there is an issue with AT49LH004-33JC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT49LH004-33JC part is unused and in its original packaging.
Return procedure for AT49LH004-33JC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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