Microchip Technology AT86RF232-ZXR
- Part No.:
- AT86RF232-ZXR
- Manufacturer:
- Microchip Technology
- Category:
- RF Transceiver ICs
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
AT86RF232-ZXR.pdf
- Description:
- IC RF TXRX 802.15.4 32QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT86RF232-ZXR from Microchip Technology (formerly Atmel) is a 2.4GHz IEEE 802.15.4-compliant radio transceiver IC designed for ZigBee, RF4CE, and 6LoWPAN systems. It integrates differential RF front-end, 128-byte frame buffer, hardware AES-128 engine, MAC acceleration (CSMA-CA, auto-ACK), and antenna diversity control. Operates from 1.8V to 3.6V with -100dBm sensitivity and programmable output power (-17dBm to +3dBm), enabling coin-cell-powered wireless sensor nodes and residential automation endpoints.
For engineers reviewing the AT86RF232-ZXR datasheet, AT86RF232-ZXR pinout, AT86RF232-ZXR application, or AT86RF232-ZXR equivalent, this page delivers verified specifications, validated SPI interface behavior, confirmed 32-pin QFN package mapping, real-world timing role in IEEE 802.15.4 PHY/MAC layering, and precise alternative selection guidance for low-power 2.4GHz ISM band designs.
Technical Context
The AT86RF232-ZXR implements an O-QPSK modulator with half-sine pulse shaping and 32-length spreading per IEEE 802.15.4-2011. Its fractional-N PLL supports fast frequency hopping and achieves <0.4ms wake-up time. The analog baseband includes LNA, PPF, BPF, limiter, and ADC with RSSI generation, while digital baseband handles time/frequency synchronization and frame buffering.
Hardware MAC acceleration offloads CSMA-CA backoff, automatic acknowledgment, retransmission, and address filtering from the host MCU. The dedicated AES-128 engine operates in parallel with PHY transactions (except SLEEP state), and true random number generation supports secure key derivation. Antenna diversity is implemented via DIG1/DIG2 outputs controlling external RF switches.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Frequency Band | 2.4GHz ISM band (2400–2483.5MHz); fully compliant with IEEE 802.15.4-2011, EN 300 328, FCC Part 15. |
| Receiver Sensitivity | -100dBm at 250kbps; enables robust link budget for battery-powered mesh nodes in noisy environments. |
| Output Power Range | Programmable from -17dBm to +3dBm in 1dB steps; allows range/power trade-off tuning without external PA. |
| Supply Voltage | 1.8V to 3.6V; internal 1.8V LDOs for AVDD/DVDD reduce external regulator count for coin-cell operation. |
| Current Consumption | SLEEP = 0.4µA, TRX_OFF = 330µA, RX_ON = 11.8mA, BUSY_TX = 13.8mA; optimized for ultra-low duty-cycle sensor applications. |
| Interface | 4-wire SPI (SCLK/MOSI/MISO/SEL) with IRQ and SLP_TR control lines; requires only two GPIOs beyond SPI for full functionality. |
| Frame Buffer | 128-byte SRAM; stores one full IEEE 802.15.4 frame (max 127 bytes PSDU + PHR), eliminating host RAM overhead. |
Pinout & Package
AT86RF232-ZXR uses a 32-pin QFN package (5mm × 5mm × 0.9mm) with exposed thermal paddle electrically connected to AVSS. Pin layout separates analog (AVSS/AVDD/XTAL1/XTAL2/RFP/RFN) and digital (DVSS/DVDD/SCLK/MISO/MOSI/IRQ) domains; strict PCB ground partitioning is required for RF performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RFP / RFN | Differential RF I/O | 100Ω differential port for TX/RX; no external switch needed; DC bias varies by state (0.9V in TX, 20mV in RX, 0V otherwise). |
| /RST | Digital input | Active-low hardware reset; internally pulled up in P_ON state; must be held high during normal operation. |
| SLP_TR | Digital input | Multi-function control: sleep/wake enable, TX start trigger, and state transition initiator; internally pulled down. |
| /SEL | Digital input | Active-low SPI chip select; enables MISO driver when asserted; internally pulled up. |
| IRQ | Digital output | Configurable active-high/low interrupt; signals frame buffer empty, RX_START, or TX_DONE events. |
| DIG1 / DIG2 | Digital output | Antenna diversity RF switch control (DIG1/DIG2 complementary); also support RX/TX frame timestamping and battery monitoring. |
| XTAL1 / XTAL2 | Analog I/O | Crystal oscillator interface (16MHz typical); XTAL1 accepts external clock; parasitic capacitance ≤3pF critical for stability. |
| CLKM | Digital output | Master clock output (1MHz typical); usable as MCU clock source or timing reference; requires 680Ω + 2.2pF low-pass filter if used. |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 802.15.4 Hardware Acceleration | On-chip FCS computation, CCA, RSSI/ED/LQI measurement, and automated ACK/CSMA-CA reduce MCU firmware complexity and latency. |
| AES-128 Security Engine | Dedicated hardware accelerator accessible via SPI; operates in parallel with PHY operations (except SLEEP), enabling concurrent encryption and RF activity. |
| Antenna Diversity Support | DIG1/DIG2 outputs drive external RF switches; algorithm selects optimal antenna path during RX, improving link reliability in multipath environments. |
| Ultra-Low-Power Sleep Mode | 0.4µA quiescent current with fast <0.4ms wake-up; enables years of operation on CR2032 batteries in periodic sensor reporting. |
| Single-Crystal Reference Architecture | Integrated crystal oscillator with XTAL1/XTAL2 pins eliminates need for external clock generator; supports 16MHz fundamental-mode crystals. |
Applications
| Smart Home Sensor Node | ZigBee Remote Control |
|---|---|
Use Scenario: Battery-powered temperature/humidity sensor transmitting data every 5 minutes to a ZigBee coordinator in HVAC monitoring. IC Role / Device Role / Timing Role: PHY/MAC layer transceiver handling O-QPSK modulation, frame assembly, hardware FCS, and CSMA-CA backoff per IEEE 802.15.4-2011. Use Value: 0.4µA sleep current extends CR2032 life beyond 5 years; -100dBm sensitivity ensures reliable reception despite wall attenuation. | Use Scenario: RF4CE-compliant TV remote using 2.4GHz for low-latency button press transmission without line-of-sight constraints. IC Role / Device Role / Timing Role: Low-latency transceiver with <0.4ms wake-up and hardware auto-ACK, minimizing user-perceived response delay. Use Value: BUSY_TX = 13.8mA at +3dBm enables strong signal penetration through furniture; integrated AES secures pairing commands. |
| Industrial Wireless Sensor Network | Healthcare Wearable Monitor |
Use Scenario: Mesh-connected vibration sensors on factory equipment reporting anomaly data to gateway via ZigBee PRO stack. IC Role / Device Role / Timing Role: IEEE 802.15.4-2011 compliant node supporting beacon-enabled superframe structure and guaranteed time slots. Use Value: Hardware address filtering and frame buffering reduce host MCU processing load; antenna diversity mitigates metal-reflection interference. | Use Scenario: Disposable glucose monitor patch transmitting encrypted readings to smartphone via 6LoWPAN-over-ZigBee. IC Role / Device Role / Timing Role: Secure transceiver performing true random number generation for session keys and AES-128 encryption of medical data. Use Value: On-chip TRNG and parallel AES eliminate external crypto ICs, reducing BoM cost and board area in space-constrained wearable design. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 2.4GHz IEEE 802.15.4 transceiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CC2531F256RHAR | Integrated 8051 MCU core; higher RX sensitivity (-97dBm); no hardware AES; 40-pin QFN. | Requires less external MCU logic but lacks standalone transceiver flexibility; larger footprint. | Select when system-level integration (MCU+RF) reduces BoM count and PCB area is not constrained. |
| JN5169-001-M00 | 32-bit RISC CPU; supports ZigBee 3.0 and Thread; -95dBm sensitivity; external flash required. | Higher protocol stack capability but greater power consumption (RX_ON = 21mA); targets gateway-class devices. | Select for multi-protocol (ZigBee/Thread) edge routers where compute headroom and software flexibility outweigh ultra-low-power needs. |
Compared with CC2531F256RHAR and JN5169-001-M00, the AT86RF232-ZXR provides the lowest sleep current (0.4µA vs ≥1µA), smallest QFN footprint (5×5mm vs 6×6mm/7×7mm), and dedicated hardware AES-making it optimal for cost-sensitive, battery-limited endpoint nodes requiring long service life and cryptographic security.
Availability
AT86RF232-ZXR is available at Aetrix Electronics and suitable for smart home sensor nodes, ZigBee remote controls, and industrial wireless sensor networks requiring stable component supply, consistent parametric performance across production lots, and long-term lifecycle assurance.
Supply support for AT86RF232-ZXR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full product support, documentation, and manufacturing continuity for the AT86RF232-ZXR.
The AT86RF232-ZXR belongs to Microchip's legacy 2.4GHz IEEE 802.15.4 transceiver portfolio, engineered specifically for ultra-low-power, cost-optimized wireless endpoints in ZigBee, RF4CE, and 6LoWPAN ecosystems.
FAQ
What is the operating voltage range for the AT86RF232-ZXR?
The AT86RF232-ZXR operates from 1.8V to 3.6V supply voltage. It integrates dual on-chip LDO regulators generating 1.8V for analog (AVDD) and digital (DVDD) domains, enabling direct coin-cell (e.g., CR2032) operation without external regulators. DVDD and AVDD outputs are available for powering external circuitry, and external supplies (DEVDD/EVDD) may bypass the regulators when required.
Does the AT86RF232-ZXR support hardware AES encryption?
Yes, the AT86RF232-ZXR includes a dedicated stand-alone 128-bit AES engine accessible via SPI. It operates in parallel with all PHY transactions except during SLEEP state, allowing concurrent encryption/decryption and RF activity. This hardware acceleration eliminates MCU overhead for security-critical applications like healthcare wearables and smart home device pairing.
How many pins does the AT86RF232-ZXR use and what is its package type?
The AT86RF232-ZXR uses a 32-pin QFN package measuring 5mm × 5mm × 0.9mm with an exposed thermal paddle. Pin assignments strictly separate analog (RFP/RFN/XTAL1/XTAL2/AVDD/AVSS) and digital (SCLK/MISO/MOSI/IRQ/SLP_TR) domains. The exposed paddle must be soldered to the PCB ground plane for thermal stability and electrical reference integrity.
What is the receiver sensitivity and maximum output power of the AT86RF232-ZXR?
The AT86RF232-ZXR achieves -100dBm receiver sensitivity at 250kbps O-QPSK modulation and supports programmable output power from -17dBm to +3dBm in 1dB increments. This combination delivers industry-leading link budget for battery-powered mesh nodes, enabling reliable communication over 100+ meters in open field and through multiple interior walls.
Can the AT86RF232-ZXR operate without an external crystal?
No, the AT86RF232-ZXR requires an external 16MHz fundamental-mode crystal connected to XTAL1 and XTAL2 pins for RF carrier generation and timing accuracy. While XTAL1 can accept an external clock signal, crystal operation is mandatory for IEEE 802.15.4 compliance and stable 2.4GHz channel spacing. Load capacitors (typically 12pF) and minimal trace parasitics (<3pF) are critical for oscillator stability.
AT86RF232-ZXR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- TxRx Only
- RF Family/Standard:
- 802.15.4, General ISM > 1GHz
- Protocol:
- 6LoWPAN, Zigbee®
- Modulation:
- O-QPSK
- Frequency:
- 2.4GHz
- Data Rate (Max):
- 250kbps
- Power - Output:
- 3dBm
- Sensitivity:
- -100dBm
- Memory Size:
- 128B SRAM
- Serial Interfaces:
- SPI
- GPIO:
- -
- Voltage - Supply:
- 1.8V ~ 3.6V
- Current - Receiving:
- 11.3mA ~ 11.8mA
- Current - Transmitting:
- 7.2mA ~ 13.8mA
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 32-QFN (5x5)
AT86RF232-ZXR FAQ
1.How can I place an order for AT86RF232-ZXR through Aetrix?
Please submit a Request for Quotation (RFQ) for AT86RF232-ZXR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT86RF232-ZXR reliable?
The price and inventory of AT86RF232-ZXR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT86RF232-ZXR is usually 5 days.
3.What payment methods are accepted for AT86RF232-ZXR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT86RF232-ZXR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT86RF232-ZXR?
AT86RF232-ZXR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT86RF232-ZXR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT86RF232-ZXR?
For technical support, including AT86RF232-ZXR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT86RF232-ZXR requirements.
6.How does Aetrix verify that AT86RF232-ZXR is sourced from the original manufacturer or authorized distributors?
All AT86RF232-ZXR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT86RF232-ZXR meets industry standards.
7.What is the process for return or replacement of AT86RF232-ZXR?
All AT86RF232-ZXR units undergo pre-shipment inspection (PSI). If there is an issue with AT86RF232-ZXR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT86RF232-ZXR part is unused and in its original packaging.
Return procedure for AT86RF232-ZXR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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