Microchip Technology ATDS2120SN
- Part No.:
- ATDS2120SN
- Manufacturer:
- Microchip Technology
- Category:
- Software, Services
- Package:
- Datasheet:
-
ATDS2120SN.pdf
- Description:
- DESIGN SYS PWRVW SCHEMATIC ENTRY
- Quantity:
- Payment:

- Shipping:

Inventory:2,646
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Product details
Overview
ATDS2120SN from Atmel is a Sun workstation-based FPGA Physical Design System for AT6000 Series FPGAs, integrating Powerview Schematic Entry and Viewlogic Simulator with 20K gate capacity. It supports full design flow - schematic capture, functional simulation, macro generation, automatic placement & routing, timing analysis, and bitstream generation - on Sun SPARC platforms running SunOS 4.1.2+ with X-Windows.
For engineers reviewing the ATDS2120SN datasheet, ATDS2120SN application, ATDS2120SN equivalent, or ATDS2120SN system requirements, this package delivers production-grade physical design capability for high-complexity AT6000 FPGA implementations on Sun workstations, including floor planning, interactive layout editing, and 100% logical path coverage timing analysis.
Technical Context
The ATDS2120SN implements a complete front-to-back FPGA design environment tailored for Sun SPARC systems, combining ViewDraw (schematic entry), ViewSim (gate-level simulation), and Atmel's proprietary back-end tools. It uses a unified database to eliminate data translation between logic entry and physical implementation stages.
It enables automatic macro generation for datapath functions (e.g., multipliers, adders) with reported worst-case speed, area, and power consumption. Timing analysis includes setup/hold violation detection and speed-critical path identification, with full back-annotation support for functional and timing simulation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Target FPGA Family | AT6000 Series - supports architecture-specific place-and-route, bitstream generation, and PROM file output for these SRAM-based FPGAs. |
| Gate Capacity Support | 20K gates - defines maximum logic density for synthesis, placement, and timing closure within the toolset. |
| Host Platform | Sun SPARC workstation - requires SunOS 4.1.2 or later, X-Windows/OpenWindows, 32 MB RAM, 40 MB disk space, CD-ROM. |
| Design Entry Method | Powerview (ViewDraw) schematic capture - provides graphical netlist creation compatible with Atmel's macro libraries and P&R engine. |
| Simulation Capability | Viewlogic ViewSim gate-level simulation - enables functional verification pre- and post-layout using vendor-matched models. |
| Timing Analysis Coverage | 100% logical path coverage - identifies all timing paths without requiring user-defined test vectors; reports setup/hold violations. |
Availability
ATDS2120SN is available at Aetrix Electronics and suitable for FPGA prototyping, academic research labs, and industrial embedded development requiring stable component supply, long-term toolchain continuity, and Sun-based CAE infrastructure support.
Supply support for ATDS2120SN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation was a U.S.-based semiconductor company specializing in microcontrollers, FPGAs, and programmable logic solutions before its acquisition by Microchip Technology in 2016.
The ATDS2120SN belongs to Atmel's AT6000 Integrated Development System product line, designed specifically to enable full-cycle physical design of AT6000 SRAM-based FPGAs on Sun workstation platforms with industry-standard CAE interoperability.
FAQ
What operating system and hardware does ATDS2120SN require?
ATDS2120SN requires a Sun SPARC workstation running SunOS 4.1.2 or higher, with X-Windows or OpenWindows support, 32 MB RAM, 40 MB free disk space, and a CD-ROM drive. It does not run on Linux, Solaris x86, or modern SPARC systems without binary compatibility layers.
Does ATDS2120SN include a prototype kit?
No, ATDS2120SN does not include a prototype kit. Prototype kits were bundled only with PC-based packages (e.g., ATDS2120PC) and University versions explicitly state exclusion. ATDS2120SN is software-only; hardware such as ATDH2080 must be ordered separately.
Is ATDS2120SN compatible with modern Sun hardware or virtualized environments?
ATDS2120SN was certified only for legacy Sun SPARC workstations (e.g., SS-10, SS-20) under SunOS 4.1.x. It is not natively compatible with Solaris 2.x+, SPARC T-series, or QEMU/Solaris emulation; successful operation requires original hardware or verified binary-compatible emulation setups.
What third-party CAE tools integrate with ATDS2120SN?
ATDS2120SN supports interface packages for Exemplar (ATDS2140SN), Mentor (ATDS2150SN), Synopsys (ATDS2160SN), Cadence Verilog/Concept (ATDS2170SN), and Integraph (ATDS2180SN), enabling synthesis and simulation interoperability while retaining Atmel's P&R and bitstream generation.
What maintenance options are available for ATDS2120SN?
Annual maintenance for ATDS2120SN is provided under ordering code ATDM2120SN, covering technical support, software updates, and bug fixes. The first year is included with purchase; renewals are optional and do not extend to University or HP variants.
ATDS2120SN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Packaging:
- -
- Product Status:
- Obsolete
- Type:
- Integrated Development Environment (IDE)
- Applications:
- -
- Edition:
- -
- License Length:
- -
- License - User Details:
- -
- Operating System:
- -
- For Use With/Related Products:
- ATF15xx
- Media Delivery Type:
- -
ATDS2120SN FAQ
1.How can I place an order for ATDS2120SN through Aetrix?
Please submit a Request for Quotation (RFQ) for ATDS2120SN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATDS2120SN reliable?
The price and inventory of ATDS2120SN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATDS2120SN is usually 5 days.
3.What payment methods are accepted for ATDS2120SN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATDS2120SN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATDS2120SN?
ATDS2120SN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATDS2120SN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATDS2120SN?
For technical support, including ATDS2120SN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATDS2120SN requirements.
6.How does Aetrix verify that ATDS2120SN is sourced from the original manufacturer or authorized distributors?
All ATDS2120SN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATDS2120SN meets industry standards.
7.What is the process for return or replacement of ATDS2120SN?
All ATDS2120SN units undergo pre-shipment inspection (PSI). If there is an issue with ATDS2120SN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATDS2120SN part is unused and in its original packaging.
Return procedure for ATDS2120SN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ATDS2120SN Tags
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