Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Embedded > CPLDs (Complex Programmable Logic Devices)

Microchip Technology ATF1504AS-10JC84

Name: ATF1504AS-10JC84
Brand: Microchip Technology
SKU: ATF1504AS-10JC84
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: ATF1504AS-10JC84

Manufacturer:: Microchip Technology

Category:: CPLDs (Complex Programmable Logic Devices)

Package:: 84-LCC (J-Lead)

Datasheet:: ATF1504AS-10JC84.pdf

Description:: IC CPLD 64MC 10NS 84PLCC

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,362

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

ATF1504AS-10JC84 from Microchip (formerly Atmel) is a high-density, electrically-erasable Complex Programmable Logic Device (CPLD) with 64 macrocells, 5 product terms per macrocell (expandable to 40), and 7.5 ns pin-to-pin delay. It operates up to 125 MHz in registered mode, supports JTAG-based in-system programming (ISP), and is packaged in an 84-lead PLCC for industrial temperature range (–40°C to +85°C) applications including legacy PCI bus interface logic and embedded control state machines.

For engineers reviewing the ATF1504AS-10JC84 datasheet, ATF1504AS-10JC84 pinout, ATF1504AS-10JC84 application, or ATF1504AS-10JC84 equivalent, key selection criteria include its 84-pin PLCC footprint, dual-voltage I/O (3.3 V / 5.0 V), programmable slew rate, pin-keeper circuitry, and JTAG boundary-scan compliance per IEEE 1149.1a–1993.

Technical Context

The ATF1504AS-10JC84 implements a hierarchical CPLD architecture with four logic blocks, each fed by a global bus carrying all 68 I/O signals plus buried feedback from all 64 macrocells. Its switch matrix selects up to 40 signals per block, enabling high-fan-in sum-of-products logic synthesis with cascade chains supporting up to 40 product terms.

Each macrocell integrates configurable D/T/latch flip-flops, individual output enable via dedicated OE pins or product terms, programmable open-collector outputs, and fast registered input paths. Three global clock inputs (GCLK1–GCLK3), input transition detection (ITD), and VCC power-up reset with selectable hysteresis provide deterministic initialization and timing control.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Density	64 macrocells - provides gate count equivalent to ~2000 usable gates for integrating TTL/SSI/MSI logic functions.
Pin-to-pin Delay	7.5 ns (–10 speed grade) - enables reliable operation at 100 MHz system clocks with timing margin.
Max Registered Frequency	125 MHz - supports high-speed synchronous control logic such as bus arbitration and protocol state machines.
I/O Voltage Support	3.3 V or 5.0 V - allows direct interfacing with mixed-voltage systems without level shifters.
Power-down Current	<10 mA - reduces standby power in battery-backed or low-power embedded systems when PD1/PD2 asserted.
Data Retention	20 years - ensures nonvolatile configuration persistence across product lifecycle without refresh.
ESD Protection	2000 V HBM - meets industrial handling robustness requirements without external protection.

Pinout & Package

ATF1504AS-10JC84 is housed in an 84-lead Plastic Leaded Chip Carrier (PLCC) package with 0.050" lead pitch and JEDEC MS-026AC standard dimensions (29.31 mm × 29.31 mm). The package supports reflow and wave soldering and is rated for industrial temperature operation (–40°C to +85°C).

Pin	Circuit Role	Design Meaning
1–11, 13–22, 24–32, 34–43, 45–54, 56–65, 67–76, 78–84	I/O	Bi-directional user-configurable logic pins; support programmable slew rate, open-collector, and pin-keeper options.
12, 23, 33, 44, 55, 66, 77	GND	Ground reference for signal integrity and power distribution; multiple GND pins reduce ground bounce.
26, 40, 51, 61, 71, 75	VCCIO	I/O power supply pins - independently biasable at 3.3 V or 5.0 V to match interfaced logic families.
37, 47	VCCINT	Core logic voltage supply - requires 5.0 V ±10% for internal array operation.
58, 68	PD1 / PD2	Power-down control inputs - drive high to enter sub-10 mA standby; disable I/O functionality during active power-down.
69	GCLK1	Global clock input 1 - feeds all macrocells; supports fast input path and ITD circuit for glitch filtering.
70	GCLR	Global asynchronous clear - resets all registers synchronously or asynchronously depending on macrocell configuration.
72	OE1	Output enable 1 - globally controls output drivers for groups of macrocells; configurable per-macrocell via product term.
73	GCLK2 / OE2	Multi-function pin - selectable as second global clock or secondary output enable signal.
74	GCLK3 / I/O	Multi-function pin - operates as third global clock or general-purpose I/O; enables flexible clock domain partitioning.
17, 27, 38, 48	TDI / TMS / TDO / TCK	JTAG test access port - enables IEEE 1149.1a-compliant boundary-scan testing and in-system programming without device removal.

Key Features

Feature	Design Value
In-system programmability (ISP)	Enables field firmware updates and design iteration via JTAG without board rework or socketing.
Programmable pin-keeper circuits	Eliminates need for external pull-ups on unused inputs/I/Os, reducing BOM cost and DC power draw.
Per-macrocell reduced-power bit	Lowers dynamic power consumption selectively for inactive logic sections, improving thermal management.
Three independent global clock inputs	Supports multi-clock domain designs (e.g., PCI bus clock + local controller clock + watchdog timer clock).
Input transition detection (ITD)	Filters metastability and glitches on critical control inputs like reset or interrupt lines before sampling.
Security fuse + 16-bit User Signature	Prevents unauthorized cloning while allowing traceability via project ID, revision, or date stamp.

Applications

PCI Bus Interface Logic	Legacy Industrial Controller
Use Scenario: Implementing address decoding, bus arbitration, and protocol handshaking for add-in cards in PCI-based industrial PCs. IC Role / Device Role / Timing Role: Configurable glue logic replacing discrete 74-series components and fixed-function PLDs. Use Value: Meets PCI electrical specs (high-drive, low skew) while enabling late-stage logic changes via ISP without PCB respin.	Use Scenario: Replacing aging PAL/GAL devices in programmable logic controllers (PLCs) operating in harsh factory environments. IC Role / Device Role / Timing Role: State machine engine for I/O scanning, safety interlock sequencing, and analog signal conditioning control. Use Value: Industrial temperature rating (–40°C to +85°C), 20-year data retention, and pin-keeper circuits ensure long-term reliability without external biasing.
Embedded Bootloader Sequencer	Test Equipment Pattern Generator
Use Scenario: Managing power-up reset sequencing, FPGA configuration loading, and memory initialization in SoM-based edge devices. IC Role / Device Role / Timing Role: Synchronous control hub coordinating multiple power rails and configuration interfaces (SPI, JTAG). Use Value: VCC power-up reset with large-hysteresis option guarantees deterministic register initialization even under slow-ramp supply conditions.	Use Scenario: Generating precise stimulus patterns and capture timing for ATE systems validating mixed-signal ASICs. IC Role / Device Role / Timing Role: High-speed pattern sequencer with sub-10 ns timing resolution and deterministic I/O toggle behavior. Use Value: 7.5 ns pin-to-pin delay and 125 MHz registered operation enable accurate generation of >100 MHz test vectors with minimal jitter.

PCI Bus Interface Logic

Legacy Industrial Controller

Use Scenario: Implementing address decoding, bus arbitration, and protocol handshaking for add-in cards in PCI-based industrial PCs.

IC Role / Device Role / Timing Role: Configurable glue logic replacing discrete 74-series components and fixed-function PLDs.

Use Value: Meets PCI electrical specs (high-drive, low skew) while enabling late-stage logic changes via ISP without PCB respin.

Use Scenario: Replacing aging PAL/GAL devices in programmable logic controllers (PLCs) operating in harsh factory environments.

IC Role / Device Role / Timing Role: State machine engine for I/O scanning, safety interlock sequencing, and analog signal conditioning control.

Use Value: Industrial temperature rating (–40°C to +85°C), 20-year data retention, and pin-keeper circuits ensure long-term reliability without external biasing.

Embedded Bootloader Sequencer

Test Equipment Pattern Generator

Use Scenario: Managing power-up reset sequencing, FPGA configuration loading, and memory initialization in SoM-based edge devices.

IC Role / Device Role / Timing Role: Synchronous control hub coordinating multiple power rails and configuration interfaces (SPI, JTAG).

Use Value: VCC power-up reset with large-hysteresis option guarantees deterministic register initialization even under slow-ramp supply conditions.

Use Scenario: Generating precise stimulus patterns and capture timing for ATE systems validating mixed-signal ASICs.

IC Role / Device Role / Timing Role: High-speed pattern sequencer with sub-10 ns timing resolution and deterministic I/O toggle behavior.

Use Value: 7.5 ns pin-to-pin delay and 125 MHz registered operation enable accurate generation of >100 MHz test vectors with minimal jitter.

Equivalent & Alternatives

The following parts are listed as comparable options for similar CPLD-based logic integration applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ATF1504AS-10JU84	Same logic architecture and pinout, but in 84-lead TQFP (JEDEC MO-152) instead of PLCC; no through-hole mounting capability.	Suitable for surface-mount-only production; lacks PLCC's socket compatibility and mechanical robustness for field-replaceable modules.	Select ATF1504AS-10JU84 only if board assembly uses SMT exclusively and thermal/mechanical stress on PLCC sockets is a concern.
EPM7064STC100-10	Intel MAX 7000S CPLD with 64 macrocells, 100-pin TQFP, 10 ns tPD; requires 5 V core, no 3.3 V I/O option.	Higher pin count and fixed 100-pin footprint; lacks programmable slew rate, pin-keeper, and ITD features present in ATF1504AS-10JC84.	Choose EPM7064STC100-10 only when existing PCB layout reserves 100-pin TQFP space and 3.3 V I/O compatibility is not required.

Compared with ATF1504AS-10JU84 and EPM7064STC100-10, the ATF1504AS-10JC84 uniquely combines through-hole PLCC packaging, dual-voltage I/O, integrated pin-keeper circuits, and input transition detection-making it optimal for industrial retrofits, test fixtures, and applications requiring field serviceability and mixed-voltage interoperability.

Availability

ATF1504AS-10JC84 is available at Aetrix Electronics and suitable for PCI interface logic, industrial PLC upgrades, embedded boot sequencing, and ATE pattern generation requiring stable component supply across extended product lifecycles.

Supply support for ATF1504AS-10JC84 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology acquired Atmel in 2016 and maintains full support for the ATF1504AS family, including datasheets, programming tools, and long-term supply commitments for industrial-grade PLDs.

The ATF1504AS series was designed specifically for high-reliability, field-upgradable logic replacement in legacy systems-emphasizing in-system programmability, industrial temperature operation, and robustness against voltage transients and ESD.

FAQ

What is the maximum operating frequency of the ATF1504AS-10JC84 in registered mode?

The ATF1504AS-10JC84 supports a maximum registered clock frequency of 125 MHz, as verified by its –10 speed grade AC characterization (fCNT = 125 MHz). This value is measured under industrial temperature conditions with VCCIO = 5.0 V and accounts for worst-case routing delays and macrocell setup/hold timing. The ATF1504AS-10JC84 achieves this performance using three global clock inputs and optimized flip-flop control paths, making it suitable for real-time control loops and high-speed bus interfaces.

Does the ATF1504AS-10JC84 support both 3.3 V and 5.0 V I/O signaling?

Yes, the ATF1504AS-10JC84 supports dual-voltage I/O operation: VCCIO pins may be biased at either 3.0–3.6 V or 4.75–5.25 V, enabling direct interface with both 3.3 V and 5.0 V logic families without external level shifters. Each I/O bank is independently configurable, and the device maintains full timing specification compliance-including VOL/VOH levels and AC parameters-at both voltage ranges. This capability is explicitly validated in the DC and AC Characteristics tables of the official Microchip datasheet for ATF1504AS-10JC84.

How does the pin-keeper feature function on the ATF1504AS-10JC84?

The pin-keeper circuit on the ATF1504AS-10JC84 actively holds the last driven logic state (high or low) on any configured input or I/O pin after it becomes floating, preventing indeterminate voltage levels that cause shoot-through current and noise. Enabled per-pin during programming, it eliminates the need for external pull-up/down resistors-reducing BOM cost, board area, and static power dissipation. This feature is especially valuable in industrial systems where unconnected I/Os may exist due to modular backplane configurations or field wiring variations.

Can the ATF1504AS-10JC84 be programmed in-system without removing it from the PCB?

Yes, the ATF1504AS-10JC84 supports full in-system programming (ISP) via its dedicated 4-pin JTAG interface (TCK, TMS, TDI, TDO), compliant with IEEE Std. 1149.1a–1993. Programming can be performed using Microchip's official tools or third-party JTAG-compatible programmers without device removal, socketing, or special voltage programming supplies. The JTAG port remains functional even when security fuse is programmed, and the ATF1504AS-10JC84 ships pre-erased and ready for immediate ISP deployment.

What are the power management capabilities of the ATF1504AS-10JC84?

The ATF1504AS-10JC84 offers three-tiered power management: (1) automatic µA standby in "L" versions (not applicable to -10JC84), (2) pin-controlled 1 mA power-down mode activated by PD1/PD2 assertion, and (3) per-macrocell reduced-power bit that cuts dynamic current for unused logic sections. All modes preserve register and output states during low-power entry/exit. These features are documented in the Power-up Reset, Speed/Power Management, and Power-down Mode sections of the ATF1504AS-10JC84 datasheet and validated across industrial temperature range.

ATF1504AS-10JC84 Specifications

Product attributes: Attribute value

Manufacturer:: Microchip Technology

Series:: ATF15xx

Package/Case:: 84-LCC (J-Lead)

Packaging:: Tube

Product Status:: Obsolete

Programmable:: Not Verified

Programmable Type:: In System Programmable (min 10K program/erase cycles)

Delay Time tpd(1) Max:: 10 ns

Voltage Supply - Internal:: 4.75V ~ 5.25V

Number of Logic Elements/Blocks:: -

Number of Macrocells:: 64

Number of Gates:: -

Number of I/O:: 64

Operating Temperature:: 0°C ~ 70°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 84-PLCC (29.31x29.31)

ATF1504AS-10JC84 FAQ

1.How can I place an order for ATF1504AS-10JC84 through Aetrix?

Please submit a Request for Quotation (RFQ) for ATF1504AS-10JC84 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ATF1504AS-10JC84 reliable?

The price and inventory of ATF1504AS-10JC84 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATF1504AS-10JC84 is usually 5 days.

3.What payment methods are accepted for ATF1504AS-10JC84?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATF1504AS-10JC84 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ATF1504AS-10JC84?

ATF1504AS-10JC84 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ATF1504AS-10JC84 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ATF1504AS-10JC84?

For technical support, including ATF1504AS-10JC84 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATF1504AS-10JC84 requirements.

6.How does Aetrix verify that ATF1504AS-10JC84 is sourced from the original manufacturer or authorized distributors?

All ATF1504AS-10JC84 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATF1504AS-10JC84 meets industry standards.

7.What is the process for return or replacement of ATF1504AS-10JC84?

All ATF1504AS-10JC84 units undergo pre-shipment inspection (PSI). If there is an issue with ATF1504AS-10JC84, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ATF1504AS-10JC84 part is unused and in its original packaging.

Return procedure for ATF1504AS-10JC84:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…