Microchip Technology ATF750C-15JC
- Part No.:
- ATF750C-15JC
- Manufacturer:
- Microchip Technology
- Package:
- 28-LCC (J-Lead)
- Datasheet:
-
ATF750C-15JC.pdf
- Description:
- IC CPLD 10MC 15NS 28PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:3,918
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ATF750C-15JC from Atmel is a high-performance, electrically-erasable Complex Programmable Logic Device (CPLD) in a 28-pin PLCC package, delivering 15 ns maximum pin-to-pin delay at 5V operation, 20 D/T-type flip-flops, and 171 total product terms - enabling implementation of complex state machines and logic replacement in space-constrained industrial control systems.
For engineers reviewing the ATF750C-15JC datasheet, ATF750C-15JC pinout, ATF750C-15JC application, or ATF750C-15JC equivalent, this device serves as a speed- and feature-upgraded replacement for ATV750B/L and ATV750/L in legacy PLD designs requiring reprogrammability, pin-keeper I/Os, and mixed clocking (product-term or direct-pin), especially where industrial temperature range (-40°C to +85°C) and RoHS-compliant green packaging are required.
Technical Context
The ATF750C-15JC implements a 22-input × 20-output CPLD architecture with 42 array inputs, 20 sum terms, and fully independent feedback paths per flip-flop. Its logic array supports both combinatorial and registered outputs, with individual asynchronous reset and synchronous preset lines across all 20 registers.
It features dual clocking modes: product-term-controlled clocks (with dedicated clock product terms per flip-flop) and direct input-pin clocking (via Pin 1/CLK), enabling heterogeneous timing domains within one device. All 10 I/O pins support programmable pin-keeper circuits to eliminate floating inputs and external pull-ups.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Pin-to-Pin Delay | 15 ns at 5V - guarantees deterministic timing for high-speed glue logic in industrial microcontroller interfaces. |
| Logic Density | 171 product terms / 20 sum terms - enables replacement of multiple discrete SSI/MSI logic ICs or older 22V10-based PLDs. |
| Flip-flop Count & Type | 20 individually configurable D- or T-type registers - supports JK/SR emulation and buried state machines without external logic. |
| I/O Configuration | 10 bi-directional I/O pins with programmable pin-keeper - eliminates need for external pull resistors and reduces board-level noise and power. |
| Operating Range | -40°C to +85°C industrial grade - validated for use in motor drives, PLC modules, and instrumentation without derating. |
| Power Supply | 5V ±5% - compatible with standard TTL/CMOS logic rails; standby current ≤180 mA (typical). |
| Data Retention | 20 years - ensures long-term reliability in unattended embedded systems without battery backup. |
Pinout & Package
ATF750C-15JC is housed in a 28-lead Plastic J-Leaded Chip Carrier (PLCC) package (JEDEC MS-018 AB), with 1.27 mm pitch, 12.32 mm × 12.32 mm body, and lead coplanarity ≤0.102 mm. Pin 1 is marked by a corner notch; pins 1, 8, 15, and 22 may be left unconnected but yield superior performance when tied to VCC (pin 1) and GND (pins 8, 15, 22).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | CLK/IN | Dedicated clock input or general logic input; supports direct-pin clocking for selected flip-flops. |
| Pins 2–11, 13–14, 23–28 | IN | 12 dedicated logic inputs; all feed into programmable interconnect array. |
| Pins 15–22 | I/O | 10 bi-directional I/O pins; each supports programmable pin-keeper and individual output enable. |
| Pin 12 | GND | Ground reference for analog and digital sections; decoupling recommended adjacent to pin. |
| Pin 24 | VCC | +5V supply; requires local 0.1 µF ceramic decoupling capacitor. |
Key Features
| Feature | Design Value |
|---|---|
| Reprogrammable EEPROM-based logic | Enables in-system logic updates without socket removal; supports ≥1000 erase/write cycles. |
| Individual D/T-type flip-flop configuration | Per-register selection allows optimal product term usage - e.g., T-mode for counters, D-mode for pipeline stages. |
| Dual clock source per flip-flop | Each register chooses between product-term clock (flexible timing control) or direct CLK pin (minimal latency). |
| Programmable pin-keeper on all I/Os | Prevents floating states on unused pins - eliminates external pull resistors and associated DC power loss. |
| Power-up reset with monotonic VCC detection | Guarantees known initial state for all 20 registers; critical for deterministic boot behavior in safety-critical logic. |
Applications
| Industrial Motor Control Interface | Legacy System Glue Logic Replacement |
|---|---|
Use Scenario: Interfacing microcontrollers to stepper/servo drivers with timing-critical enable, direction, and step signals. IC Role / Device Role / Timing Role: Registered logic sequencer generating synchronized pulse trains and status handshaking with 15 ns timing precision. Use Value: Replaces 3–4 discrete 74-series ICs while supporting field-upgradable timing parameters via JEDEC reprogramming. |
Use Scenario: Upgrading aging 22V10-based control logic in telecom line cards without PCB redesign. IC Role / Device Role / Timing Role: Drop-in functional superset providing identical pinout and JEDEC compatibility with enhanced density and clocking flexibility. Use Value: Enables addition of diagnostic registers and fault-handling logic without changing footprint or layout. |
| Programmable Power Sequencing Controller | Test Equipment Signal Conditioning |
Use Scenario: Generating precise power-on reset delays and voltage-rail enable sequences for multi-rail FPGA or DSP systems. IC Role / Device Role / Timing Role: State machine implementing cascaded delay chains with asynchronous reset and synchronous preset for deterministic initialization. Use Value: Eliminates RC-based timing inaccuracies and provides traceable, repeatable sequencing across temperature and voltage variations. |
Use Scenario: Adapting signal levels and timing between legacy test instruments (TTL) and modern DUTs (LVCMOS). IC Role / Device Role / Timing Role: Bi-directional level translator with programmable slew rate control and glitch-free bus arbitration. Use Value: Supports mixed-voltage test setups using single-device I/O pin-keeper logic instead of discrete translators and pull-ups. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable logic applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATF750C-10JU | 10 ns max propagation delay; same 28J PLCC package and industrial temperature range. | Higher-speed option for designs requiring tighter setup/hold margins or >55 MHz fMAXS operation. | Select when timing closure demands sub-15 ns path delays; otherwise ATF750C-15JC offers optimal cost/performance balance. |
| ATF750CL-15JU | Low-power "L" variant with 1 mA standby current; identical 15 ns speed grade and PLCC-28 package. | Targeted for battery-powered or thermally constrained industrial handhelds where quiescent power dominates system budget. | Choose only if standby current <2 mA is mandatory; ATF750C-15JC delivers higher drive strength and broader voltage tolerance. |
Compared with ATF750C-10JU, the ATF750C-15JC trades 5 ns of speed for lower cost and relaxed timing margin requirements; compared with ATF750CL-15JU, it sacrifices ultra-low standby current for stronger output drive (±40 mA vs ±1 mA) and wider VCC operating tolerance (±5% vs ±10%).
Availability
ATF750C-15JC is available at Aetrix Electronics and suitable for industrial motor control interface, legacy system glue logic replacement, programmable power sequencing controller, and test equipment signal conditioning requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for ATF750C-15JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and programmable logic devices for industrial, automotive, and consumer applications.
The ATF750C family was designed as a high-density, reprogrammable CPLD solution targeting industrial control, instrumentation, and legacy system upgrades - emphasizing pin compatibility with 22V10, EEPROM-based field updates, and robust operation across -40°C to +85°C.
FAQ
What is the operating voltage range for ATF750C-15JC?
The ATF750C-15JC operates at 5V ±5%, with absolute maximum ratings of -0.6V to +7.0V on any pin. It is not rated for 3.3V operation; using 5V supplies ensures full compliance with VIH/VIL thresholds, output drive capability (IOH = -4 mA, IOL = 16 mA), and AC timing specifications including the 15 ns tPD guarantee. Deviation outside 4.75–5.25V invalidates published AC characteristics.
Is ATF750C-15JC pin-compatible with ATV750/L devices?
Yes, the ATF750C-15JC is a direct replacement for ATV750/L in the same PLCC-28 package (28J), maintaining identical pin functions and JEDEC file compatibility when compiled in ATV750 mode. However, full utilization of its advanced features - such as T-type flip-flops, pin-clocking, and pin-keeper - requires recompilation using Atmel WinCUPL targeting the ATF750C device model, not the legacy ATV750 subset.
Does ATF750C-15JC support in-system programming?
Yes, the ATF750C-15JC supports in-system programming via standard JEDEC file loading using compatible programmers (e.g., third-party units supporting V750 cross-programming mode). Its electrically-erasable EEPROM architecture allows full reconfiguration without removal from the PCB, provided VPP programming voltage (10.25–10.75V) and proper timing constraints (tAW ≥15 ns) are met during the programming cycle.
What is the purpose of the pin-keeper circuit in ATF750C-15JC?
The pin-keeper circuit in ATF750C-15JC actively holds unused I/O pins at their last driven logic state (high or low), preventing floating inputs that cause shoot-through current and EMI. Enabled per-pin in the fuse map, it eliminates external pull-up/pull-down resistors - reducing BOM count, board area, and static power consumption. It does not affect signal integrity during active driving.
How many product terms does ATF750C-15JC provide per output?
The ATF750C-15JC allocates two sum terms per output, with a variable format assigning four to eight product terms per sum term - yielding up to 171 total product terms across the device. This architecture allows deep logic equations per output (e.g., wide AND-OR expressions) while retaining flexibility for shared terms across multiple outputs, directly enabling complex combinational functions without external fanout.
ATF750C-15JC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- ATF750C(L)
- Package/Case:
- 28-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Verified
- Programmable Type:
- EE PLD
- Delay Time tpd(1) Max:
- 15 ns
- Voltage Supply - Internal:
- 4.75V ~ 5.25V
- Number of Logic Elements/Blocks:
- -
- Number of Macrocells:
- 10
- Number of Gates:
- -
- Number of I/O:
- 10
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-PLCC (11.51x11.51)
ATF750C-15JC FAQ
1.How can I place an order for ATF750C-15JC through Aetrix?
Please submit a Request for Quotation (RFQ) for ATF750C-15JC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATF750C-15JC reliable?
The price and inventory of ATF750C-15JC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATF750C-15JC is usually 5 days.
3.What payment methods are accepted for ATF750C-15JC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATF750C-15JC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATF750C-15JC?
ATF750C-15JC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATF750C-15JC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATF750C-15JC?
For technical support, including ATF750C-15JC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATF750C-15JC requirements.
6.How does Aetrix verify that ATF750C-15JC is sourced from the original manufacturer or authorized distributors?
All ATF750C-15JC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATF750C-15JC meets industry standards.
7.What is the process for return or replacement of ATF750C-15JC?
All ATF750C-15JC units undergo pre-shipment inspection (PSI). If there is an issue with ATF750C-15JC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATF750C-15JC part is unused and in its original packaging.
Return procedure for ATF750C-15JC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ATF750C-15JC Tags

-
5M40ZE64C5N
Intel

-
ATF1502ASV-15AU44
Microchip Technology

-
5M80ZE64C5N
Intel

-
5M80ZT100C5N
Intel

-
ATF1502AS-10AU44
Microchip Technology

-
ATF1502AS-10JU44
Microchip Technology

-
5M80ZE64I5N
Intel

-
5M80ZT100I5N
Intel
-
LC4032V-75TN48C
Lattice Semiconductor Corporation

-
ATF1504ASV-15AU44
Microchip Technology

-
ATF1504AS-10JU44
Microchip Technology

-
5M160ZE64C5N
Intel
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

.jpg)