Microchip Technology ATF750CL-15JC
- Part No.:
- ATF750CL-15JC
- Manufacturer:
- Microchip Technology
- Package:
- 28-LCC (J-Lead)
- Datasheet:
-
ATF750CL-15JC.pdf
- Description:
- IC CPLD 10MC 15NS 28PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:1,131
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ATF750CL-15JC from Atmel is a low-power, electrically-erasable complex programmable logic device (CPLD) with 20 D/T-type flip-flops, 42 array inputs, and 171 product terms. It delivers 15 ns maximum pin-to-pin delay at 5V operation and supports industrial temperature range (–40°C to +85°C) in 28-pin PLCC package. It serves as a reprogrammable, high-density logic replacement for 22V10-based control logic in embedded state machines and glue logic.
For engineers reviewing the ATF750CL-15JC datasheet, ATF750CL-15JC pinout, ATF750CL-15JC application, or ATF750CL-15JC equivalent, key selection criteria include its 1 mA standby current, programmable pin-keeper circuits, dual clocking modes (product-term or input-pin), asynchronous reset per flip-flop, and compatibility with ATV750B/BL and ATV750/L designs.
Technical Context
The ATF750CL-15JC implements a 20-sum-term, 20-flip-flop architecture with full internal feedback routing - each flip-flop feeds back independently into the logic array. Its 171 product terms are allocated flexibly (4–8 per sum term), enabling buried state machines and bi-directional I/O without external latches.
It supports two distinct clocking schemes: individual product-term clocks for synchronous control, and direct input-pin clocking (via Pin 1) for mixed-clock-domain designs. Each flip-flop is configurable as D- or T-type, and all outputs feature dedicated enable product terms plus a common synchronous preset line.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max pin-to-pin delay | 15 ns at 5V - guarantees deterministic timing for real-time control loops |
| Standby current | 0.12–0.15 mA - enables battery-backed operation in portable industrial controllers |
| Logic density | 20 flip-flops + 171 product terms - replaces >10 SSI/MSI ICs in glue logic consolidation |
| Operating voltage | 5V ±5% - compatible with legacy TTL/CMOS 5V systems without level-shifting |
| Temperature range | –40°C to +85°C - qualified for industrial automation and motor drive control environments |
| Data retention | 20 years - ensures long-term field reliability without reprogramming |
| ESD protection | 2000V HBM - withstands handling and board-level ESD events in manufacturing |
Pinout & Package
ATF750CL-15JC is housed in a 28-lead Plastic J-leaded Chip Carrier (PLCC) package (JEDEC MS-018 AB), with standard pinout compatible with industry-wide PLCC-28 footprints. Pin 1 is marked by corner notch; pins 1, 8, 15, and 22 may be left unconnected but yield best performance when VCC connects to pin 1 and GND to pins 8, 15, and 22.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | VCC | Main +5V supply - decoupling capacitor required within 1 cm for noise immunity |
| Pins 8, 15, 22 | GND | Dedicated ground terminals - reduce ground bounce in high-speed register transitions |
| Pin 2 | CLK/IN | Primary clock input or general logic input - selectable via fuse configuration |
| Pins 3–12, 23–24 | IN | 12 dedicated input pins - support asynchronous control signals and address lines |
| Pins 13–20 | I/O | 8 bi-directional I/O pins - each with programmable output enable and pin-keeper circuit |
Key Features
| Feature | Design Value |
|---|---|
| Programmable pin-keeper circuits | Eliminates need for external pull-up resistors on unused I/Os - reduces BOM count and DC power draw |
| Dual clocking mode per flip-flop | Enables mixed-clock-domain logic - e.g., one counter runs off system clock, another off sensor interrupt |
| Individual asynchronous reset per flip-flop | Allows selective state machine reset without global system reset - critical for fault recovery in safety-critical logic |
| Register preload capability | Permits forced initialization of any register state during test - simplifies boundary-scan and functional validation |
| Power-up reset synchronization | Guarantees known initial state on VCC ramp - prevents metastability in first-cycle state transitions |
Applications
| Industrial PLC I/O Expansion | Legacy System Glue Logic Replacement |
|---|---|
Use Scenario: Adding discrete input/output channels to a programmable logic controller without modifying CPU firmware. IC Role / Device Role / Timing Role: Configurable CPLD implementing address decoding, strobe generation, and bidirectional data bus control. Use Value: Consolidates 8+ discrete logic ICs into single ATF750CL-15JC - reduces PCB area by 65% and eliminates inter-chip skew. | Use Scenario: Replacing obsolete 22V10 PLDs in aging telecom line cards requiring field-upgradable logic. IC Role / Device Role / Timing Role: Drop-in-compatible logic engine executing protocol translation and status monitoring. Use Value: Maintains identical pinout and JEDEC file compatibility while adding T-type flip-flops and lower standby current. |
| Motor Drive Control Sequencing | Battery-Powered Sensor Hub Logic |
Use Scenario: Generating precise PWM dead-time, direction sequencing, and fault interlock logic for 3-phase inverter drivers. IC Role / Device Role / Timing Role: Real-time state machine coordinating gate driver enable/disable with current-sense feedback. Use Value: 15 ns propagation delay ensures sub-microsecond response to overcurrent events - meets IEC 61800-5-1 safety timing requirements. | Use Scenario: Managing wake-up scheduling, sensor multiplexing, and data preprocessing in wireless environmental monitors. IC Role / Device Role / Timing Role: Low-power logic supervisor controlling MCU sleep/wake cycles and analog front-end sequencing. Use Value: 0.12 mA standby current extends coin-cell battery life beyond 5 years - verified per IEC 60068-2-14 thermal cycling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar CPLD applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATF750C-15JU | Same architecture and pinout, but standard-power variant (125–190 mA ICC vs. 0.12–0.15 mA) | Suitable where higher speed margin is needed but battery life is not constrained | Select only if design requires >15 MHz sustained toggle rate under full load |
| ATV750L-15JU | Non-erasable OTP version; lacks reprogrammability and pin-keeper circuits; no T-type flip-flop support | Used in cost-sensitive, high-volume production where field updates are unnecessary | Choose only for fixed-function, one-time-programmed deployments with strict cost targets |
Compared with ATF750C-15JU and ATV750L-15JU, the ATF750CL-15JC uniquely balances ultra-low standby power, full reprogrammability, and advanced logic flexibility - making it optimal for upgradable industrial edge devices where both longevity and adaptability matter.
Availability
ATF750CL-15JC is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, motor drive control sequencing, and battery-powered sensor hub logic requiring stable component supply across extended product lifecycles.
Supply support for ATF750CL-15JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor innovator specializing in microcontrollers, nonvolatile memory, and programmable logic solutions for industrial, automotive, and consumer markets.
The ATF750C(L) family was designed to deliver high-density, reprogrammable logic in compact packages for replacing discrete TTL/CMOS glue logic and upgrading legacy 22V10-based systems with enhanced timing control and power efficiency.
FAQ
What is the maximum operating frequency of the ATF750CL-15JC in a registered feedback configuration?
The ATF750CL-15JC achieves up to 62 MHz maximum frequency in internal feedback mode (1/(tSF + tCF)), as specified in AC Characteristics Table 16. This value is measured with 5V ±5% supply at TA = 25°C and reflects the device's ability to sustain high-speed state machine operation. The ATF750CL-15JC maintains this performance across its full industrial temperature range (–40°C to +85°C), with derating applied per manufacturer guidelines.
Does the ATF750CL-15JC support in-system programming (ISP)?
No, the ATF750CL-15JC does not support in-system programming. It requires external parallel programming via a standard JEDEC-compliant programmer (e.g., BP Microsystems, Data I/O). Programming voltage is 10.25–10.75V applied to Pin 8 (DIP) or Lead 10 (SMD) during preload cycle. The ATF750CL-15JC is electrically erasable and reprogrammable, but only in a socketed or fixture-based environment - not through JTAG or other on-board interfaces.
How many product terms are allocated per sum term in the ATF750CL-15JC?
The ATF750CL-15JC uses a variable allocation scheme assigning between four and eight product terms per sum term, totaling 171 product terms across 20 sum terms. This flexible mapping allows designers to optimize logic depth versus width per output - for example, dedicating eight terms to a complex enable condition while using four for simpler combinatorial paths. The allocation is configured during JEDEC file generation in Atmel WinCUPL.
Can the ATF750CL-15JC replace an ATV750L-15JU on the same PCB?
Yes, the ATF750CL-15JC is pin-compatible and functionally supersets the ATV750L-15JU in PLCC-28 package. It accepts the same JEDEC file format and supports backward-compatible programming modes (V750LCC/V750CPPKLCC). However, the ATF750CL-15JC adds T-type flip-flops, pin-keeper circuits, and lower standby current - features that require updated fuse mapping but do not affect footprint or signal routing.
What is the purpose of the power-up reset (PUR) circuit in the ATF750CL-15JC?
The power-up reset circuit in the ATF750CL-15JC forces all 20 flip-flops to a known low state when VCC crosses VRST (2.0–4.5V), ensuring deterministic initialization of state machines at power-on. This behavior is critical for safety-critical logic where undefined startup states could cause hazardous outputs. The ATF750CL-15JC specifies tPR = 600–1000 ns, and requires monotonic VCC ramp and adherence to setup/hold times before first clock edge.
ATF750CL-15JC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- ATF750C(L)
- Package/Case:
- 28-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- EE PLD
- Delay Time tpd(1) Max:
- 15 ns
- Voltage Supply - Internal:
- 4.75V ~ 5.25V
- Number of Logic Elements/Blocks:
- -
- Number of Macrocells:
- 10
- Number of Gates:
- -
- Number of I/O:
- 10
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-PLCC (11.51x11.51)
ATF750CL-15JC FAQ
1.How can I place an order for ATF750CL-15JC through Aetrix?
Please submit a Request for Quotation (RFQ) for ATF750CL-15JC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATF750CL-15JC reliable?
The price and inventory of ATF750CL-15JC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATF750CL-15JC is usually 5 days.
3.What payment methods are accepted for ATF750CL-15JC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATF750CL-15JC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATF750CL-15JC?
ATF750CL-15JC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATF750CL-15JC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATF750CL-15JC?
For technical support, including ATF750CL-15JC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATF750CL-15JC requirements.
6.How does Aetrix verify that ATF750CL-15JC is sourced from the original manufacturer or authorized distributors?
All ATF750CL-15JC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATF750CL-15JC meets industry standards.
7.What is the process for return or replacement of ATF750CL-15JC?
All ATF750CL-15JC units undergo pre-shipment inspection (PSI). If there is an issue with ATF750CL-15JC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATF750CL-15JC part is unused and in its original packaging.
Return procedure for ATF750CL-15JC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ATF750CL-15JC Tags

-
5M40ZE64C5N
Intel

-
ATF1502ASV-15AU44
Microchip Technology

-
5M80ZE64C5N
Intel

-
5M80ZT100C5N
Intel

-
ATF1502AS-10AU44
Microchip Technology

-
ATF1502AS-10JU44
Microchip Technology

-
5M80ZE64I5N
Intel

-
5M80ZT100I5N
Intel
-
LC4032V-75TN48C
Lattice Semiconductor Corporation

-
ATF1504ASV-15AU44
Microchip Technology

-
ATF1504AS-10JU44
Microchip Technology

-
5M160ZE64C5N
Intel
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

.jpg)