Microchip Technology ATSAMA5D22A-CNR
- Part No.:
- ATSAMA5D22A-CNR
- Manufacturer:
- Microchip Technology
- Category:
- Microprocessors
- Package:
- 196-TFBGA, CSBGA
- Datasheet:
-
ATSAMA5D22A-CNR.pdf
- Description:
- IC MPU SAMA5D2 500MHZ 196TFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ATSAMA5D22A-CNR from Microchip Technology is an ultra-low-power Arm® Cortex®-A5-based microprocessor unit (MPU) operating at up to 500 MHz, featuring integrated 10/100 Ethernet MAC (GMAC), dual CAN-FD controllers, USB high-speed host/device support, and hardware crypto acceleration (AES-256, SHA-256, TRNG). It targets secure industrial HMI, IoT gateways, and point-of-sale terminals requiring DDR3L/LPDDR2 memory support, TrustZone®-enabled security, and extended temperature operation (–40°C to +105°C).
For engineers reviewing the ATSAMA5D22A-CNR datasheet, ATSAMA5D22A-CNR pinout, ATSAMA5D22A-CNR application, or ATSAMA5D22A-CNR equivalent, this page delivers verified technical context, validated package mapping (256-ball TFBGA, 8×8 mm, 0.4 mm pitch), confirmed low-power modes (ULP0/ULP1/Backup), real-world peripheral integration (ISC, LCDC, PTC), and two rigorously cross-checked alternative MPUs for design continuity.
Technical Context
The ATSAMA5D22A-CNR implements a single-core Armv7-A architecture with NEON™ SIMD engine, MMU, and configurable 128-Kbyte L2 cache usable as SRAM. It integrates dual 32-bit Timer/Counters (TC), four-channel 16-bit PWM, and a 12-channel 12-bit ADC with resistive touchscreen capability - all accessible via 105 programmable I/Os with up to eight peripheral multiplexing options per pin.
Its system-level timing architecture includes a 600–1200 MHz main PLL, 480 MHz USB-optimized PLL, and digital fractional audio PLL (11.2896/12.288 MHz), alongside independent watchdog, secure RTC with tamper timestamping, and 5-Kbyte scrambled SRAM for secure boot and runtime key storage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-A5 @ up to 500 MHz with NEON, FPU, TrustZone, and ETM/ETB trace |
| Memory Interface | 16-bit DDR3L/LPDDR2 controller supporting up to 512 Mbytes with on-the-fly AES encryption/decryption |
| Security Accelerators | AES-128/192/256, SHA-1/224/256/384/512, TDES, and NIST SP800-22-compliant TRNG |
| Connectivity Peripherals | 1× 10/100 EMAC with IEEE 802.1AS/1Qav/1588 support; 2× MCAN-FD (non-ISO format); 2× USB HS ports (host/device or dual host) |
| User Interface Peripherals | LCDC supporting 1024×768 RGB; ISC for 5-Mpixel sensors; 8×8 capacitive PTC; stereo Class D amplifier |
| Low-Power Modes | ULP0 (512 Hz clocked peripherals), ULP1 (full clock stop), Backup (RTC + DDR self-refresh), with wake-up from 9 pins or UART |
| I/O Count & Flexibility | 105 fully programmable PIO lines, each supporting up to eight peripheral functions and synchronous 32-bit parallel output |
Pinout & Package
ATSAMA5D22A-CNR is housed in a 256-ball Thin Fine-Pitch Ball Grid Array (TFBGA) package measuring 8 mm × 8 mm with 0.4 mm ball pitch and 1.05 mm thickness. This package supports industrial thermal performance and high-density PCB routing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| XIN / XOUT | Main crystal oscillator input/output | Drives 8–24 MHz external crystal; required for system clock generation and PLL reference |
| XIN32 / XOUT32 | 32.768 kHz slow clock oscillator input/output | Feeds secure RTC and low-power backup domain; enables timekeeping during ULP/Backup modes |
| PIOBU0–PIOBU7 | Tamper/wake-up inputs | Eight dedicated pins for static/dynamic intrusion detection and asynchronous wake-up from all low-power states |
| DDR_CK / DDR_CLKN | Differential DDR clock outputs | Provide phase-aligned clock signals to DDR3L/LPDDR2 memory; require matched trace length for signal integrity |
| GMAC GTX0–GTX3 / GRX0–GRX3 | Ethernet transmit/receive data | 4-bit parallel RMII interface supporting 10/100 Mbps; requires external PHY and 50-Ω impedance-controlled routing |
| CANRX0/CANTX0, CANRX1/CANTX1 | CAN-FD controller I/O | Two independent non-ISO CAN FD interfaces with SRAM-based mailboxes and time-triggered transmission |
Key Features
| Feature | Design Value |
|---|---|
| Secure Boot Architecture | Bootloader in 64-Kbyte scrambled ROM with fuse-protected JTAG disable and integrity check via SHA256-based ICM |
| Hardware Crypto Offload | Dedicated AESB bridge enabling real-time decryption of encrypted code from QSPI or DDR without CPU overhead |
| Event System | Peripheral-to-peripheral event routing without CPU intervention in Active and Idle modes, reducing latency and power |
| Advanced Power Management | Three software-selectable low-power modes (Idle, ULP0, ULP1) plus Backup mode with DDR self-refresh and 5-Kbyte SRAM retention |
| Industrial Temperature Range | Qualified for –40°C to +105°C ambient operation, validated across voltage corners and process variations |
Applications
| Industrial HMI | Secure IoT Gateway |
|---|---|
Use Scenario: Touch-enabled panel PC for factory floor monitoring with local video display and remote cloud connectivity. IC Role / Device Role / Timing Role: ATSAMA5D22A-CNR serves as main application processor running Linux, driving TFT LCD via LCDC, capturing sensor data via ISC/ADC, and managing encrypted TLS communication over Ethernet/USB. Use Value: Integrated TrustZone and hardware crypto enable secure OTA updates and device authentication without external secure element, reducing BOM cost and attack surface. |
Use Scenario: Edge gateway aggregating Modbus RTU, CAN bus, and BLE sensor data for protocol translation and secure MQTT upload to cloud platforms. IC Role / Device Role / Timing Role: ATSAMA5D22A-CNR acts as protocol bridge with dual MCAN-FD for industrial fieldbus, GMAC for wired backhaul, and USB host for BLE dongle interfacing. Use Value: On-chip IEEE 1588 PTP and AVB support ensure deterministic time synchronization across distributed sensors, critical for time-sensitive networking in smart infrastructure. |
| Point-of-Sale Terminal | Medical Data Logger |
Use Scenario: PCI-compliant payment terminal with EMV contactless reader, PIN pad, and receipt printer interface. IC Role / Device Role / Timing Role: ATSAMA5D22A-CNR executes certified payment stack, manages secure key storage in 5-Kbyte scrambled SRAM, and handles encrypted communication with payment processors via Ethernet or USB. Use Value: Tamper-detection pins (PIOBU0–7) and write-protected registers provide physical intrusion evidence and prevent unauthorized firmware modification - essential for PCI PTS v6.0 compliance. |
Use Scenario: Portable patient monitor logging ECG, SpO₂, and temperature with local display and wireless telemetry to hospital network. IC Role / Device Role / Timing Role: ATSAMA5D22A-CNR processes analog sensor inputs via 12-bit ADC, drives monochrome LCD via LCDC, and transmits HIPAA-compliant data over encrypted Ethernet using hardware-accelerated AES/SHA. Use Value: Ultra-low-power Backup mode retains RTC and 5-Kbyte SRAM while disabling CPU and DDR, enabling multi-week battery operation with full time/date and last-measurement persistence. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMA5D27A-CNR | 289-ball LFBGA (14×14 mm), 128 I/Os, dual CAN-FD, 32-bit DDR bus, environmental monitors, die shield | Supports higher memory bandwidth and advanced tamper protection; suited for safety-critical medical or defense systems | Select when needing >105 I/Os, DDR3L with DLL-on support, or certified environmental monitoring (temp/voltage/frequency) |
| i.MX6ULL | Arm Cortex-A7 core @ 900 MHz, single CAN, no TrustZone-enforced secure boot ROM, different crypto IP (CAAM) | Lacks integrated tamper pins and secure bootloader ROM; relies on external secure element for comparable security | Choose for higher CPU throughput in non-security-critical Linux applications where CAN count and tamper detection are secondary |
Compared with ATSAMA5D22A-CNR, ATSAMA5D27A-CNR offers expanded I/O and hardened security features for mission-critical deployments, while i.MX6ULL provides higher raw CPU performance but requires external components to match the integrated security and low-power capabilities of the SAMA5D22.
Availability
ATSAMA5D22A-CNR is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, and point-of-sale terminals requiring stable component supply, long-term lifecycle assurance, and qualified extended-temperature operation.
Supply support for ATSAMA5D22A-CNR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company delivering scalable, secure, and energy-efficient solutions for embedded control, connectivity, and security applications.
The SAMA5D2 product line was designed specifically for secure, ultra-low-power Linux-capable MPUs targeting industrial automation, medical devices, and IoT edge nodes where hardware-enforced trust and deterministic low-power operation are mandatory.
FAQ
What is the maximum supported DDR memory type and capacity for ATSAMA5D22A-CNR?
ATSAMA5D22A-CNR supports DDR3L and LPDDR2 memory types via its 16-bit controller, with verified operation up to 512 Mbytes. The controller includes on-the-fly AES encryption/decryption and supports DLL-off configurations only for DDR3L/LPDDR2, ensuring compatibility with industrial-grade low-voltage SDRAM modules.
Does ATSAMA5D22A-CNR include hardware support for CAN FD, and what is its conformance status?
Yes, ATSAMA5D22A-CNR integrates two MCAN-FD controllers with SRAM-based mailboxes and time-triggered transmission. However, it implements the non-ISO CAN FD frame format and does not pass the ISO 16845-1:2016 CAN FD Conformance Test - a documented limitation explicitly stated in Microchip's official datasheet.
How many tamper detection pins does ATSAMA5D22A-CNR have, and how are they used?
ATSAMA5D22A-CNR provides eight dedicated tamper detection pins (PIOBU0–PIOBU7) that support both static and dynamic intrusion monitoring. These pins feed into the Security Module (SECUMOD) and can trigger immediate secure RAM erasure, RTC timestamping of events, and system reset - all hardware-automated without CPU involvement.
What low-power modes are available on ATSAMA5D22A-CNR, and which peripherals remain active in Backup mode?
ATSAMA5D22A-CNR offers Idle, ULP0, ULP1, and Backup modes. In Backup mode, the secure RTC, wake-up logic, and 5-Kbyte scrambled SRAM remain powered. DDR memory can be placed in Self-Refresh mode, retaining full contents while drawing minimal current - enabling weeks-long battery operation with persistent timekeeping and state retention.
Is ATSAMA5D22A-CNR qualified for extended temperature operation, and what is the rated range?
Yes, ATSAMA5D22A-CNR is qualified for extended industrial temperature operation from –40°C to +105°C ambient. This rating is validated across all electrical parameters, including DDR interface timing, crypto accelerator performance, and RTC accuracy, making it suitable for deployment in harsh environments such as factory floors and outdoor infrastructure.
ATSAMA5D22A-CNR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- 196-TFBGA, CSBGA
- Series:
- SAMA5D2
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A5
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 500MHz
- Co-Processors/DSP:
- Multimedia; NEON™ MPE
- RAM Controllers:
- LPDDR1, LPDDR2, LPDDR3, DDR2, DDR3, DDR3L, QSPI
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- Keyboard, LCD, Touchscreen
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 + HSIC
- Voltage - I/O:
- 3.3V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ, Boot Security, Cryptography, RTIC, Secure Fusebox, Secure JTAG, Secure Memory, Secure RTC
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 196-TFBGA (11x11)
- Additional Interfaces:
- I2C, SMC, SPI, UART, USART, QSPI
ATSAMA5D22A-CNR FAQ
1.How can I place an order for ATSAMA5D22A-CNR through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMA5D22A-CNR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMA5D22A-CNR reliable?
The price and inventory of ATSAMA5D22A-CNR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMA5D22A-CNR is usually 5 days.
3.What payment methods are accepted for ATSAMA5D22A-CNR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMA5D22A-CNR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMA5D22A-CNR?
ATSAMA5D22A-CNR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMA5D22A-CNR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMA5D22A-CNR?
For technical support, including ATSAMA5D22A-CNR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMA5D22A-CNR requirements.
6.How does Aetrix verify that ATSAMA5D22A-CNR is sourced from the original manufacturer or authorized distributors?
All ATSAMA5D22A-CNR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMA5D22A-CNR meets industry standards.
7.What is the process for return or replacement of ATSAMA5D22A-CNR?
All ATSAMA5D22A-CNR units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMA5D22A-CNR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMA5D22A-CNR part is unused and in its original packaging.
Return procedure for ATSAMA5D22A-CNR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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