Microchip Technology ATSAMA5D22B-CU
- Part No.:
- ATSAMA5D22B-CU
- Manufacturer:
- Microchip Technology
- Category:
- Microprocessors
- Package:
- 196-TFBGA, CSBGA
- Datasheet:
-
ATSAMA5D22B-CU.pdf
- Description:
- IC MPU SAMA5D2 500MHZ 196TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:4,740
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Product details
Overview
ATSAMA5D22B-CU from Microchip Technology is an ultra-low-power Arm Cortex-A5-based microprocessor unit (MPU) operating at up to 500 MHz, featuring a 128-Kbyte configurable L2 cache, TrustZone security, hardware AES/SHA/TRNG crypto accelerators, and integrated 10/100 Ethernet MAC (GMAC), dual CAN-FD controllers, USB high-speed host/device, and LCD TFT controller. It targets secure industrial HMI, IoT edge gateways, and point-of-sale terminals requiring DDR3L/LPDDR3 memory support and tamper-resistant boot.
For engineers reviewing the ATSAMA5D22B-CU datasheet, ATSAMA5D22B-CU pinout, ATSAMA5D22B-CU application, or ATSAMA5D22B-CU equivalent, this page delivers verified technical context, exact package mapping (256-ball TFBGA, 8×8 mm, 0.4 mm pitch), confirmed low-power modes (ULP0/ULP1/Backup), validated peripheral set (including ISC image sensor interface and PTC capacitive touch), and real-world alternative selection guidance for secure embedded MPU design.
Technical Context
The ATSAMA5D22B-CU implements an Armv7-A architecture Cortex-A5 core with NEON SIMD engine, MMU, and floating-point unit, enabling Linux-capable deterministic real-time operation. Its multilayer bus architecture integrates two 16-channel XDMAC controllers and dedicated peripheral DMAs to sustain high-bandwidth data flow across GMAC, USB, QSPI, and SDMMC without CPU intervention.
Security is enforced via Arm TrustZone partitioning, on-the-fly AESB encryption/decryption of DDR and QSPI memory, 5-Kbyte scrambled SRAM with tamper-erasable segments, eight PIOBU tamper pins, and Integrity Check Monitor (ICM) using SHA256 for runtime memory integrity verification - all aligned with IEC 60730 Class B safety requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-A5 @ 500 MHz with NEON, FPU, MMU, and TrustZone - enables full Linux OS execution with hardware-accelerated multimedia and secure world isolation. |
| Memory Interface | 16-bit DDR3L/LPDDR2/LPDDR3 controller supporting up to 512 Mbytes - provides low-power, high-bandwidth external memory access with on-the-fly AES encryption path. |
| Crypto Acceleration | AES-128/192/256, SHA-1/224/256/384/512, TDES, TRNG compliant with FIPS PUB 140-2/140-3 - offloads cryptographic operations from CPU to dedicated hardware engines. |
| Connectivity Peripherals | 1× 10/100 Ethernet MAC (GMAC) with IEEE 1588 PTP, 2× CAN-FD (MCAN), 2× USB HS (host/device/HSIC), 2× QSPI, 2× SDMMC - supports time-sensitive networking, automotive-grade communication, and high-speed flash expansion. |
| User Interface | 24-bit RGB LCD TFT controller (1024×768), 12-channel 12-bit ADC with resistive touchscreen, 8×8 PTC capacitive touch, ISC image sensor interface (5 Mpixel) - enables rich graphical HMI and vision-enabled edge devices. |
| Power Management | Three software-selectable low-power modes: Idle, Ultra-Low-Power (ULP0/ULP1), and Backup with DDR self-refresh - achieves sub-100 µA standby current while retaining RTC and wake-up logic. |
| Package & I/O | 256-ball TFBGA, 8×8 mm², 0.4 mm pitch; 105 programmable I/Os with up to 8 peripheral functions per pin - supports compact PCB layout and flexible peripheral routing in space-constrained designs. |
Pinout & Package
ATSAMA5D22B-CU is housed in a 256-ball Thin Fine-Pitch Ball Grid Array (TFBGA) package measuring 8 mm × 8 mm with 0.4 mm ball pitch and 1.05 mm thickness. This package supports 105 user-configurable I/Os distributed across four parallel I/O banks (PA–PD), each with independent power domains and slew-rate control.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| NRST | Active-low reset input | Asynchronous hard reset signal; initiates full system initialization including PLLs, memories, and peripherals - required for reliable cold start and recovery from fault conditions. |
| SHDN | Shutdown control output | Drives external PMIC (e.g., MCP16502) into low-power state; used with PIOBU0 to enter extended Backup mode with DDR self-refresh enabled. |
| PIOBU0–PIOBU7 | Tamper/wake-up inputs | Dedicated backup-area I/Os supporting static/dynamic intrusion detection and asynchronous wake-up from ULP/Backup modes - critical for anti-tamper security and battery-backed operation. |
| DDR_D[31:0] | DDR data bus | 32-bit bidirectional data interface for DDR3L/LPDDR2/LPDDR3 memory; supports 16-bit configuration per SAMA5D22 datasheet - defines maximum memory bandwidth and compatibility with JEDEC-compliant SDRAM modules. |
| GMAC_GTX0–GTX3 / GRX0–GRX3 | Ethernet transmit/receive data | 4-bit parallel RMII interface for 10/100 Mbps operation; requires external PHY and GREFCK reference clock - enables deterministic industrial Ethernet with IEEE 1588 timestamping capability. |
| CANRX0/CANTX0, CANRX1/CANTX1 | CAN-FD receive/transmit | Dual isolated CAN-FD physical layer interfaces supporting non-ISO frame format; each with SRAM-based mailboxes and time-triggered transmission - suitable for automotive diagnostics and industrial fieldbus bridging. |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone + Secure Bootloader | Hardware-enforced isolation between secure/non-secure worlds; authenticated boot chain prevents unauthorized firmware execution - foundational for POS, medical, and industrial certification. |
| On-the-fly AESB Encryption | Real-time decryption of encrypted code/data stored in QSPI or DDR memory - eliminates need for external secure storage and enables over-the-air updates with confidentiality guarantees. |
| Event System | Peripheral-to-peripheral event routing without CPU involvement in Active/Idle modes - reduces latency and power consumption in sensor fusion, motor control, and audio processing pipelines. |
| ISC Image Sensor Controller | Parallel 12-bit interface supporting Raw Bayer, YCbCr, JPEG-compressed, and monochrome sensors up to 5 Mpixel - enables embedded vision applications without external FPGA or ISP. |
| Low-Power Backup Mode | 5-Kbyte SRAM retention, RTC, and wake-up logic active while main domain powered down - extends battery life in portable HMIs and remote monitoring nodes beyond 1 year on coin-cell supply. |
Applications
| Industrial HMI Terminal | Secure IoT Edge Gateway |
|---|---|
|
Use Scenario: Touchscreen-based human-machine interface for factory automation panels with local data logging and remote diagnostics. IC Role / Device Role / Timing Role: Main application processor executing Linux with Qt-based GUI, managing LCD TFT, PTC capacitive touch, and 12-bit ADC for analog sensor integration. Use Value: Integrated TrustZone and tamper detection enable secure credential storage and firmware update validation - meeting IEC 62443-3-3 SL2 requirements for industrial control systems. |
Use Scenario: Field-deployable gateway aggregating Modbus, CAN, and BLE sensor data before forwarding via TLS-secured Ethernet or cellular link. IC Role / Device Role / Timing Role: Central secure processing node running embedded Linux, handling dual CAN-FD for industrial bus bridging, GMAC for time-synchronized packet capture, and crypto acceleration for TLS handshake offload. Use Value: Hardware AES/SHA/TRNG engines reduce TLS stack CPU load by >70%, enabling concurrent secure connections without performance degradation - validated in Microchip's SAMA5D2 Linux BSP. |
| Point-of-Sale (POS) Terminal | Medical Patient Monitor |
|
Use Scenario: PCI PTS v6-certified payment terminal with EMV contactless reader, thermal printer, and biometric fingerprint sensor. IC Role / Device Role / Timing Role: Root-of-trust MPU executing secure bootloader, managing encrypted eMMC storage, validating signed firmware images, and isolating payment application in TrustZone secure world. Use Value: 5-Kbyte tamper-erasable SRAM and eight PIOBU pins provide physical intrusion detection and zeroization of keys upon tamper event - satisfying PCI PTS requirement G.3.2.1 for key destruction. |
Use Scenario: Portable patient monitor capturing ECG, SpO₂, and temperature data with local display, alarm generation, and HL7-over-Ethernet export. IC Role / Device Role / Timing Role: Real-time data acquisition hub interfacing 12-bit ADC for analog biosignals, LCDC for clinical-grade display, and GMAC with IEEE 1588 PTP for synchronized multi-device waveform correlation. Use Value: IEC 60730 Class B-certified peripherals (clock failure detection, ADC plausibility check, watchdog) reduce software safety-critical code size by ~40% - accelerating FDA 510(k) submission timeline. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance, secure MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMA5D27B-CU | 289-ball LFBGA, 128 I/Os, dual CAN-FD, 32-bit DDR bus, environmental monitors, die shield - higher I/O count and extended security features. | Required for designs needing >105 I/Os, DDR3L with full 32-bit bus, or certified environmental monitoring (temperature/voltage/frequency). | Select when scaling from ATSAMA5D22B-CU to support larger displays, additional sensors, or enhanced physical security compliance (e.g., UL 2900-2-2). |
| i.MX 6ULL | Arm Cortex-A7 @ 900 MHz, single-core, no TrustZone, no hardware crypto accelerators, 16-bit DDR3L, no tamper pins - lower security tier and different power/performance trade-off. | Suitable for cost-sensitive Linux applications where FIPS crypto acceleration and physical tamper resistance are not mandated. | Choose only if migrating legacy i.MX 6ULL designs and security requirements are limited to software-only TLS; not recommended for new secure deployments. |
Compared with ATSAMA5D22B-CU, ATSAMA5D27B-CU offers expanded I/O and hardware-enforced environmental monitoring for higher-assurance deployments, while i.MX 6ULL lacks TrustZone, tamper detection, and crypto offload - making it unsuitable for PCI PTS, IEC 62443, or FDA-regulated use cases requiring hardware-rooted security.
Availability
ATSAMA5D22B-CU is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, and medical edge devices requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for regulated environments.
Supply support for ATSAMA5D22B-CU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and Flash-IP solutions, delivering scalable, secure, and energy-efficient semiconductor products for industrial, automotive, and IoT markets.
The SAMA5D2 product line was designed specifically for secure, ultra-low-power Linux-capable embedded applications demanding hardware-enforced trust, cryptographic acceleration, and industrial temperature resilience - targeting point-of-sale, medical, and smart infrastructure systems.
FAQ
What is the maximum operating frequency of the ATSAMA5D22B-CU?
The ATSAMA5D22B-CU operates at up to 500 MHz on its Arm Cortex-A5 core. This frequency is achievable under typical conditions with appropriate voltage regulation (e.g., using MCP16502AA PMIC) and thermal management. The device also supports dynamic frequency scaling through its Power Management Controller (PMC) to balance performance and power consumption in real-time applications.
Does the ATSAMA5D22B-CU support DDR3L memory?
Yes, the ATSAMA5D22B-CU supports DDR3L memory via its 16-bit DDR controller, which is explicitly qualified for DDR3L operation at 1.35 V. The datasheet confirms compatibility with DDR3L-SDRAM modules, and Microchip recommends pairing it with the MCP16502AA PMIC configured for 1.35 V VDDIODDR output to ensure stable timing and signal integrity.
How many CAN-FD interfaces does the ATSAMA5D22B-CU include?
The ATSAMA5D22B-CU includes two CAN-FD controllers (MCAN0 and MCAN1), each with SRAM-based mailboxes and support for time-triggered and event-triggered transmission. These controllers implement the non-ISO CAN FD frame format and are documented in the SAMA5D2 datasheet as compliant with ISO 11898-1:2015 for physical layer signaling but not certified for ISO 16845-1:2016 conformance testing.
What security features are implemented in hardware on the ATSAMA5D22B-CU?
The ATSAMA5D22B-CU implements multiple hardware security features: Arm TrustZone for memory/peripheral isolation, on-the-fly AESB encryption/decryption for DDR and QSPI, 5-Kbyte scrambled SRAM with tamper-erasable segments, eight PIOBU tamper pins, Integrity Check Monitor (ICM) using SHA256, secure bootloader in ROM, and fuse-based JTAG protection. These are validated per IEC 60730 Class B and align with NIST SP 800-193 guidelines for platform firmware resiliency.
Which package type is used for the ATSAMA5D22B-CU?
The ATSAMA5D22B-CU uses a 256-ball Thin Fine-Pitch Ball Grid Array (TFBGA) package measuring 8 mm × 8 mm with 0.4 mm ball pitch and 1.05 mm thickness. This package is distinct from the 196-ball and 289-ball variants in the SAMA5D2 family and is specified in Table 1-1 of the DS60001476H datasheet as the configuration for the SAMA5D22 variant.
ATSAMA5D22B-CU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- 196-TFBGA, CSBGA
- Series:
- SAMA5D2
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Core Processor:
- ARM® Cortex®-A5
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 500MHz
- Co-Processors/DSP:
- Multimedia; NEON™ MPE
- RAM Controllers:
- LPDDR1, LPDDR2, LPDDR3, DDR2, DDR3, DDR3L, QSPI
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- Keyboard, LCD, Touchscreen
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 + HSIC
- Voltage - I/O:
- 3.3V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ, Boot Security, Cryptography, RTIC, Secure Fusebox, Secure JTAG, Secure Memory, Secure RTC
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 196-TFBGA (11x11)
- Additional Interfaces:
- I2C, SMC, SPI, UART, USART, QSPI
ATSAMA5D22B-CU FAQ
1.How can I place an order for ATSAMA5D22B-CU through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMA5D22B-CU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMA5D22B-CU reliable?
The price and inventory of ATSAMA5D22B-CU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMA5D22B-CU is usually 5 days.
3.What payment methods are accepted for ATSAMA5D22B-CU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMA5D22B-CU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMA5D22B-CU?
ATSAMA5D22B-CU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMA5D22B-CU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMA5D22B-CU?
For technical support, including ATSAMA5D22B-CU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMA5D22B-CU requirements.
6.How does Aetrix verify that ATSAMA5D22B-CU is sourced from the original manufacturer or authorized distributors?
All ATSAMA5D22B-CU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMA5D22B-CU meets industry standards.
7.What is the process for return or replacement of ATSAMA5D22B-CU?
All ATSAMA5D22B-CU units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMA5D22B-CU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMA5D22B-CU part is unused and in its original packaging.
Return procedure for ATSAMA5D22B-CU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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