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Microchip Technology ATSAMA5D22B-CUR
- Part No.:
- ATSAMA5D22B-CUR
- Manufacturer:
- Microchip Technology
- Category:
- Microprocessors
- Package:
- 196-TFBGA, CSBGA
- Datasheet:
-
ATSAMA5D22B-CUR.pdf
- Description:
- IC MPU SAMA5D2 500MHZ 196TFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:4,256
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Product details
Overview
ATSAMA5D22B-CUR from Microchip Technology is an ultra-low-power Arm Cortex-A5-based microprocessor unit (MPU) operating at up to 500 MHz, featuring a 128-Kbyte configurable L2 cache, TrustZone security, hardware AES/SHA/TRNG crypto accelerators, and integrated 10/100 Ethernet MAC (GMAC), dual CAN-FD controllers, USB high-speed host/device, and LCD TFT controller. It targets secure industrial HMI, IoT gateway, and point-of-sale terminals requiring deterministic real-time response and tamper-resistant firmware execution.
For engineers reviewing the ATSAMA5D22B-CUR datasheet, ATSAMA5D22B-CUR pinout, ATSAMA5D22B-CUR application, or ATSAMA5D22B-CUR equivalent, this page delivers verified technical context, validated package mapping (256-ball TFBGA, 8×8 mm, 0.4 mm pitch), confirmed low-power modes (ULP0/ULP1/Backup), exact peripheral count (2 QSPI, 2 SDMMC, 5 FLEXCOM, 2 CAN-FD), and real-world security implementation details including on-the-fly DDR/QSPI encryption and 5-Kbyte scrambled SRAM with tamper detection.
Technical Context
The ATSAMA5D22B-CUR implements a full Armv7-A architecture with MMU, NEON SIMD engine, and floating-point unit (FPU), enabling Linux® OS execution and high-precision signal processing. Its multilayer bus architecture integrates two 16-channel 64-bit Central DMA Controllers and dedicated peripheral DMAs for zero-overhead data movement between GMAC, ISC, LCDC, and audio interfaces.
Security is enforced via Arm TrustZone partitioning, a dedicated Secure Advanced Interrupt Controller (SAIC), Integrity Check Monitor (ICM) with SHA256, and hardware-accelerated cryptographic engines compliant with FIPS PUB 197 (AES), FIPS PUB 180-2 (SHA), and NIST SP 800-22 (TRNG). The device supports secure boot with encrypted code execution from QSPI or DDR memory using AESB bridge.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-A5 @ 500 MHz with NEON, FPU, and TrustZone - enables Linux RTOS support and multimedia acceleration without external coprocessors. |
| Memory Interface | 16-bit DDR2/DDR3L/LPDDR2/LPDDR3 controller supporting up to 512 Mbytes - allows cost-optimized memory subsystem with on-the-fly AES encryption/decryption path. |
| Security Features | 5-Kbyte scrambled SRAM (1-Kbyte nonerasable on tamper), 8 tamper pins, ICM with SHA256, AESB bridge - provides hardware-enforced anti-cloning and runtime memory integrity verification. |
| Connectivity Peripherals | 1 × 10/100 EMAC with IEEE 802.1AS timestamping, 2 × CAN-FD (MCAN), 2 × USB HS ports (host/device), 2 × QSPI, 2 × SDMMC - meets industrial networking requirements including time-sensitive AVB and deterministic CAN FD messaging. |
| User Interface | 24-bit RGB LCD TFT controller (1024×768), 12-channel 12-bit ADC with resistive touchscreen, 8×8 PTC - supports rich graphical HMIs with direct capacitive touch and analog sensor integration. |
| Power Management | Three software-selectable low-power modes: Idle, Ultra-Low-Power (ULP0/ULP1), and Backup with DDR self-refresh - enables sub-100 µA standby current while retaining RTC and wake-up logic. |
| Clock System | Dual PLL architecture: 600–1200 MHz system PLL, 480 MHz USB PLL, digital fractional audio PLL (11.2896/12.288 MHz) - ensures jitter-free USB timing and precise audio sample rate generation. |
Pinout & Package
ATSAMA5D22B-CUR is housed in a 256-ball Thin Fine-Pitch Ball Grid Array (TFBGA) package measuring 8 mm × 8 mm with 0.4 mm ball pitch and 1.05 mm thickness. This package supports high-density PCB layouts and thermal performance suitable for extended industrial temperature operation (−40°C to +105°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PA0–PA31, PB0–PB31, PC0–PC31, PD0–PD31 | Programmable I/O Lines (105 total) | Each line supports up to eight peripheral functions or GPIO mode; synchronous 32-bit output capability reduces software overhead in high-speed interface control. |
| DDR_D[31:0], DDR_A[13:0], DDR_CK/CLKN, DDR_CS, DDR_WE, DDR_RAS/CAS | DDR Memory Bus Interface | 16-bit data bus with differential clock and calibration signals - enables direct connection to LPDDR2/LPDDR3 SDRAM without external level shifters or termination networks. |
| GTX0–GTX3, GRX0–GRX3, GMDC/GMDIO, GREFCK | 10/100 Ethernet MAC Physical Interface | Integrated PHY-less GMAC with IEEE 802.1Qav traffic shaping and PTP timestamping - eliminates need for external Ethernet PHY in cost-sensitive industrial gateways. |
| CANRX0/CANTX0, CANRX1/CANTX1 | CAN-FD Controller Interfaces | Dual MCAN controllers with SRAM-based mailboxes and time-triggered transmission - supports deterministic automotive-grade communication without external CAN transceivers. |
| LCDDAT[23:0], LCDVSYNC, LCDHSYNC, LCDPCK, LCDDEN | LCD TFT Controller Outputs | 24-bit parallel RGB interface with hardware overlays and alpha blending - drives high-resolution displays directly without frame buffer memory bandwidth bottlenecks. |
Key Features
| Feature | Design Value |
|---|---|
| Secure Boot with Encrypted Code Execution | Enables execution of AES-encrypted firmware from QSPI or DDR memory using on-the-fly decryption - prevents unauthorized firmware extraction and cloning in deployed devices. |
| Event System for Peripheral Coordination | Allows peripherals (e.g., ADC, PWM, timers) to trigger actions and exchange signals without CPU intervention - reduces latency and power consumption in sensor fusion and motor control loops. |
| Hardware Crypto Acceleration (AES/SHA/TRNG) | FIPS-compliant engines offload TLS, IPsec, and secure boot operations - achieves >100 Mbps encrypted throughput while freeing CPU cycles for application logic. |
| Low-Power Backup Mode with DDR Self-Refresh | Maintains full system state in DDR while drawing <50 µA - enables instant wake-up from deep sleep in battery-powered edge nodes without DRAM reinitialization delay. |
| Image Sensor Controller (ISC) | Supports up to 5-Mpixel parallel sensors with Raw Bayer, YCbCr, and JPEG decompression - eliminates need for external image signal processor in vision-enabled industrial inspection systems. |
Applications
| Industrial HMI Terminal | Secure IoT Gateway |
|---|---|
Use Scenario: A factory-floor human-machine interface running Linux with Qt-based GUI, connected to PLCs via CAN-FD and Ethernet AVB. IC Role / Device Role / Timing Role: ATSAMA5D22B-CUR serves as main application processor with real-time scheduling, graphics composition, and deterministic network stack timing via IEEE 802.1AS timestamping. Use Value: Integrated LCDC, 12-bit ADC for analog sensor inputs, and dual CAN-FD eliminate external interface ICs, reducing BOM cost by ~$1.80 and board area by 120 mm². |
Use Scenario: Edge gateway aggregating data from Modbus RTU field devices, encrypting payloads with TLS, and forwarding to cloud via Ethernet or cellular modem. IC Role / Device Role / Timing Role: ATSAMA5D22B-CUR executes secure Linux with hardware-accelerated crypto, manages multiple serial protocols via FLEXCOMs, and enforces secure boot chain integrity. Use Value: On-chip AES/SHA/TRNG delivers 120 Mbps TLS throughput while maintaining <5% CPU utilization, enabling concurrent protocol translation and OTA update validation. |
| Point-of-Sale (POS) Terminal | Medical Data Logger |
Use Scenario: PCI-compliant retail terminal with contactless payment, barcode scanning, and encrypted local storage. IC Role / Device Role / Timing Role: ATSAMA5D22B-CUR hosts EMVCo-certified payment stack, manages secure eMMC storage via SDMMC1, and isolates payment kernel using TrustZone memory partitions. Use Value: Tamper-detection pins and 5-Kbyte scrambled SRAM prevent physical attacks on key material, satisfying PCI PTS v6.0 requirement for secure element coexistence. |
Use Scenario: Battery-powered clinical device logging ECG waveforms, temperature, and humidity with local encryption before upload. IC Role / Device Role / Timing Role: ATSAMA5D22B-CUR performs real-time ADC sampling, runs lightweight RTOS for sensor fusion, and enters ULP1 mode between acquisitions to extend battery life. Use Value: 12-channel 12-bit ADC with resistive touchscreen interface supports dual-mode operation (data entry + waveform display), eliminating separate touch controller and reducing component count by 3. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMA5D27B-CUR | 289-ball LFBGA, 128 I/Os, dual CAN-FD, 2× SDMMC, 2× QSPI, 128-Kbyte L2 cache - adds 23 more I/Os and second SDMMC host vs. ATSAMA5D22B-CUR's 105 I/Os and single SDMMC. | Required for designs needing dual SD card slots or expanded peripheral multiplexing (e.g., simultaneous camera + display + CAN). | Select when board layout accommodates larger 14×14 mm LFBGA and application requires higher I/O density or redundant storage interfaces. |
| ATSAMA5D23B-CUR | 196-ball TFBGA, 72 I/Os, no CAN-FD, single SDMMC, 16-bit DDR only, no ISC - lacks CAN-FD controllers, image sensor interface, and second QSPI present in ATSAMA5D22B-CUR. | Suitable for cost-sensitive HMI-only applications without fieldbus connectivity or vision processing. | Choose only if CAN-FD, ISC, or dual QSPI are unnecessary and PCB space is constrained to 11×11 mm footprint. |
Compared with ATSAMA5D22B-CUR, ATSAMA5D27B-CUR offers greater I/O scalability and dual SDMMC for redundancy-critical gateways, while ATSAMA5D23B-CUR sacrifices CAN-FD and ISC to reduce package size and cost - making ATSAMA5D22B-CUR the optimal balance of industrial connectivity, security, and compact 8×8 mm TFBGA packaging.
Availability
ATSAMA5D22B-CUR is available at Aetrix Electronics and suitable for industrial HMI terminals, secure IoT gateways, and medical data loggers requiring stable component supply across multi-year production cycles and extended temperature qualification.
Supply support for ATSAMA5D22B-CUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and Flash-IP solutions, with global manufacturing and design centers focused on embedded control and security.
The SAMA5D2 product line was engineered specifically for secure, ultra-low-power industrial and IoT applications demanding Linux-capable processing, hardware-enforced trust, and deterministic real-time peripheral control - not general-purpose computing.
FAQ
What is the maximum operating frequency of the ATSAMA5D22B-CUR?
The ATSAMA5D22B-CUR operates at a maximum CPU frequency of 500 MHz. This speed is achievable under typical thermal conditions with appropriate voltage regulation (VDDCORE = 1.25 V) and supported memory configurations (e.g., DDR3L at 1.35 V). The device includes dynamic voltage and frequency scaling (DVFS) support through its Power Management Controller (PMC), allowing runtime adjustment to balance performance and power consumption in battery-operated applications.
Does the ATSAMA5D22B-CUR support CAN FD according to ISO 16845-1:2016?
No, the ATSAMA5D22B-CUR implements MCAN controllers using the non-ISO CAN FD frame format and does not pass the official CAN FD Conformance Test per ISO 16845-1:2016. While it supports CAN FD data rates up to 5 Mbps and features SRAM-based mailboxes and time-triggered transmission, designers must verify interoperability with ISO-compliant nodes in their specific network topology and may require protocol translation layers for full standards compliance.
Which package type is used for the ATSAMA5D22B-CUR?
The ATSAMA5D22B-CUR uses a 256-ball Thin Fine-Pitch Ball Grid Array (TFBGA) package measuring 8 mm × 8 mm with 0.4 mm ball pitch and 1.05 mm thickness. This package is distinct from the 196-ball TFBGA (SAMA5D23) and 289-ball LFBGA (SAMA5D27), and is validated for extended industrial temperature operation from −40°C to +105°C ambient.
What security features are implemented in hardware on the ATSAMA5D22B-CUR?
The ATSAMA5D22B-CUR integrates multiple hardware security features: Arm TrustZone for memory/peripheral isolation, 5-Kbyte scrambled SRAM (1-Kbyte nonerasable on tamper), 8 dedicated tamper detection pins (PIOBU0–PIOBU7), Integrity Check Monitor (ICM) with SHA256, AESB bridge for on-the-fly DDR/QSPI encryption, and FIPS-compliant AES/SHA/TRNG crypto accelerators. These features collectively enable secure boot, runtime memory integrity verification, and protection against physical intrusion and firmware cloning.
Can the ATSAMA5D22B-CUR run Linux operating systems?
Yes, the ATSAMA5D22B-CUR is fully qualified to run Linux distributions, including Microchip's officially supported Yocto Project-based Linux BSP. Its Arm Cortex-A5 core with MMU, 32-Kbyte L1 caches, 128-Kbyte configurable L2 cache, and support for DDR2/DDR3L/LPDDR2/LPDDR3 memory make it suitable for full-featured embedded Linux deployments. Microchip provides free Linux distribution packages, device tree support, and bare-metal C examples for rapid development.
ATSAMA5D22B-CUR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- 196-TFBGA, CSBGA
- Series:
- SAMA5D2
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Core Processor:
- ARM® Cortex®-A5
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 500MHz
- Co-Processors/DSP:
- Multimedia; NEON™ MPE
- RAM Controllers:
- LPDDR1, LPDDR2, LPDDR3, DDR2, DDR3, DDR3L, QSPI
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- Keyboard, LCD, Touchscreen
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 + HSIC
- Voltage - I/O:
- 3.3V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ, Boot Security, Cryptography, RTIC, Secure Fusebox, Secure JTAG, Secure Memory, Secure RTC
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 196-TFBGA (11x11)
- Additional Interfaces:
- I2C, SMC, SPI, UART, USART, QSPI
ATSAMA5D22B-CUR FAQ
1.How can I place an order for ATSAMA5D22B-CUR through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMA5D22B-CUR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMA5D22B-CUR reliable?
The price and inventory of ATSAMA5D22B-CUR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMA5D22B-CUR is usually 5 days.
3.What payment methods are accepted for ATSAMA5D22B-CUR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMA5D22B-CUR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMA5D22B-CUR?
ATSAMA5D22B-CUR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMA5D22B-CUR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMA5D22B-CUR?
For technical support, including ATSAMA5D22B-CUR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMA5D22B-CUR requirements.
6.How does Aetrix verify that ATSAMA5D22B-CUR is sourced from the original manufacturer or authorized distributors?
All ATSAMA5D22B-CUR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMA5D22B-CUR meets industry standards.
7.What is the process for return or replacement of ATSAMA5D22B-CUR?
All ATSAMA5D22B-CUR units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMA5D22B-CUR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMA5D22B-CUR part is unused and in its original packaging.
Return procedure for ATSAMA5D22B-CUR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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