Microchip Technology ATSAMA5D22C-CUR

Overview

ATSAMA5D22C-CUR from Microchip Technology is an ultra-low-power Arm Cortex-A5-based microprocessor unit (MPU) operating at up to 500 MHz, featuring a 128-Kbyte configurable L2 cache, TrustZone security, hardware AES/SHA/TRNG crypto accelerators, and integrated 10/100 Ethernet MAC (GMAC), dual CAN-FD controllers, USB host/device/HSIC, LCD TFT controller, and 12-channel 12-bit ADC with resistive touchscreen support - deployed in industrial HMI, secure IoT gateways, and point-of-sale terminals.

For engineers reviewing the ATSAMA5D22C-CUR datasheet, ATSAMA5D22C-CUR pinout, ATSAMA5D22C-CUR application, or ATSAMA5D22C-CUR equivalent, this page delivers verified technical context, validated package mapping (256-ball TFBGA, 8×8 mm, 0.4 mm pitch), confirmed low-power modes (ULP0/ULP1/Backup), real-world peripheral integration (e.g., ISC image sensor interface, PTC capacitive touch), and two rigorously cross-checked alternative MPUs for design continuity.

Technical Context

The ATSAMA5D22C-CUR implements an Armv7-A architecture Cortex-A5 core with NEON SIMD engine and floating-point unit (FPU), paired with a multilayer bus matrix supporting 2×16-channel DMA controllers for zero-overhead peripheral data transfers. Its memory subsystem includes MMU, 32-Kbyte L1 instruction/data caches, and DDR2/DDR3L/LPDDR2/LPDDR3 controller with on-the-fly AESB encryption/decryption.

Security is enforced via Arm TrustZone, 5-Kbyte scrambled SRAM (1-Kbyte tamper-erasable), eight tamper detection pins (PIOBU0–7), Integrity Check Monitor (ICM) using SHA256, and secure bootloader in 64-Kbyte masked ROM. It supports IEEE 802.1AS timestamping, AVB traffic shaping (802.1Qav), and PTP v2 for deterministic Ethernet timing.

Key Specifications

Pinout & Package

ATSAMA5D22C-CUR is housed in a 256-ball Thin Fine-Pitch Ball Grid Array (TFBGA) package measuring 8 mm × 8 mm with 0.4 mm ball pitch and 1.05 mm thickness, optimized for high-density industrial PCB layouts and thermal performance under extended temperature operation (−40°C to +105°C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar MPU-based embedded applications.

Compared with ATSAMA5D22C-CUR, ATSAMA5D27C-CUR offers expanded I/O, environmental sensing, and die shielding for certified safety applications, while i.MX6ULL trades security depth and peripheral integration for lower cost and higher single-thread CPU speed - neither is pin-compatible, requiring PCB redesign and BSP adaptation.

Availability

ATSAMA5D22C-CUR is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, and point-of-sale terminals requiring stable component supply across long-life production cycles and extended temperature operation.

Supply support for ATSAMA5D22C-CUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology is a leading provider of microcontrollers, analog components, and Flash-IP solutions, delivering silicon, development tools, and embedded firmware for industrial, automotive, and IoT markets.

The SAMA5D2 product line targets secure, ultra-low-power Linux-capable MPUs for applications demanding hardware-enforced trust, deterministic connectivity, and extended temperature reliability - exemplified by ATSAMA5D22C-CUR's integration of TrustZone, MCAN-FD, and IEEE 1588 Ethernet.

FAQ

What is the maximum operating frequency and supported memory types for ATSAMA5D22C-CUR?

ATSAMA5D22C-CUR operates at up to 500 MHz and supports DDR2, DDR3L, LPDDR2, LPDDR3, QSPI, e.MMC, and SLC/MLC NAND Flash with up to 32-bit ECC. Its 16-bit DDR bus is validated for DDR3L at 533 MT/s, and the memory controller includes on-the-fly AESB encryption for secure data access - critical for applications handling sensitive firmware or user data.

Does ATSAMA5D22C-CUR support CAN FD, and what is its conformance status?

ATSAMA5D22C-CUR integrates two MCAN controllers supporting CAN FD frame format, but explicitly implements the non-ISO variant and does not pass the ISO 16845-1:2016 CAN FD Conformance Test. It remains suitable for proprietary or vendor-specific CAN FD networks where ISO compliance is not mandated - users must validate protocol stack compatibility with their target ecosystem.

What security features are embedded in ATSAMA5D22C-CUR for secure boot and runtime protection?

ATSAMA5D22C-CUR includes a 64-Kbyte scrambled and maskable ROM embedding a secure bootloader, TrustZone-enforced memory isolation, 5-Kbyte scrambled SRAM (1-Kbyte tamper-erasable), eight PIOBU tamper pins, Integrity Check Monitor (ICM) using SHA256, and hardware AES/SHA/TRNG accelerators. These features collectively enable FIPS 140-3–aligned secure boot, runtime key protection, and firmware integrity validation - essential for PCI PTS and IEC 60730 Class B certification.

Which package type and pin count does ATSAMA5D22C-CUR use?

ATSAMA5D22C-CUR uses a 256-ball Thin Fine-Pitch Ball Grid Array (TFBGA) package measuring 8 mm × 8 mm with 0.4 mm pitch and 1.05 mm thickness. This package supports 105 GPIOs and is qualified for extended industrial temperature range (−40°C to +105°C), making it suitable for space-constrained, thermally demanding deployments such as factory automation panels and outdoor gateways.

What low-power modes are available on ATSAMA5D22C-CUR, and how do they differ?

ATSAMA5D22C-CUR offers three software-selectable low-power modes: Idle (CPU halted, peripherals active), Ultra-Low-Power (ULP0/ULP1 with clocks gated and selective wake-up sources), and Backup (RTC and wake logic active, DDR in self-refresh). ULP1 achieves sub-100 µA standby current, while Backup mode retains full RTC functionality and supports wake-up from PIOBU, UART, or analog comparator - ideal for battery-backed data loggers and emergency alert systems.