Microchip Technology ATSAMA5D23B-CN

Overview

ATSAMA5D23B-CN from Microchip Technology is a 32-bit ARM Cortex-A5-based microprocessor running at up to 500 MHz, featuring TrustZone security, 128 KB L2 cache (configurable as SRAM), 128 KB internal scrambled SRAM, and hardware crypto accelerators (AES-256, SHA-512, TRNG). It supports DDR2/DDR3/LPDDR3 memory, dual QSPI, 10/100 Ethernet MAC with AVB/PTP, two CAN-FD controllers, and a 12-channel 12-bit ADC with resistive touchscreen support - deployed in industrial HMI, secure IoT gateways, and point-of-sale terminals.

For engineers reviewing the ATSAMA5D23B-CN datasheet, ATSAMA5D23B-CN pinout, ATSAMA5D23B-CN application, or ATSAMA5D23B-CN equivalent, this page delivers verified technical context, validated package mapping (LFBGA289), confirmed pin functions per IO set, real-world low-power mode behavior (Ultra-low-power mode with SleepWalking™), and precise alternative part comparisons for secure embedded MPU selection.

Technical Context

The ATSAMA5D23B-CN implements a multilayer AXI/AHB bus matrix with two 16-channel XDMAC controllers and dedicated peripheral DMAs, enabling zero-CPU-overhead data transfers between DDR, QSPI, SDMMC, ISC, and audio peripherals. Its security architecture integrates ARM TrustZone, hardware-scrambled memories (SRAM, ROM, DDR/QSPI via AESB), Integrity Check Monitor (SHA256), tamper detection on eight PIOBU pins, and secure boot with encrypted code execution.

Power management includes three software-selectable low-power modes: Idle (CPU halted, peripherals active), Ultra-low-power mode (512 Hz clocking with SleepWalking™ event-driven wakeup), and Backup mode (RTC + wakeup logic active, DDR in self-refresh). The device features a 128 KB L2 cache configurable as SRAM, a 160 KB unscrambled ROM for NAND ECC tables, and a 64 KB scrambled maskable ROM embedding the secure boot loader.

Key Specifications

Pinout & Package

The ATSAMA5D23B-CN is packaged in a 289-ball LFBGA (14 × 14 mm, 0.8 mm pitch) with I/O grouped into functionally matched IO sets to guarantee timing integrity. Pin assignment follows strict IO-set grouping rules - mixing pins across sets invalidates timing guarantees.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-security ARM Cortex-A5 MPU applications.

Compared with ATSAMA5D23B-CN, ATSAMA5D27B-CN reduces package size and peripheral count for compact designs, while ATSAMA5D28B-CN extends its security envelope with certified environmental monitoring - both share identical core architecture, TrustZone, and AESB functionality but differ in I/O scalability and physical attack resistance.

Availability

ATSAMA5D23B-CN is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, and point-of-sale terminals requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for safety-critical deployments.

Supply support for ATSAMA5D23B-CN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog, FPGA, and security solutions, with strong focus on industrial, automotive, and IoT markets.

The SAMA5D2 series was designed as a secure, power-efficient ARM Cortex-A5 MPU family targeting applications demanding hardware-enforced trust, real-time connectivity, and robust anti-cloning protection - including POS, medical edge devices, and industrial gateways.

FAQ

What is the maximum operating frequency of the ATSAMA5D23B-CN?

The ATSAMA5D23B-CN operates at up to 500 MHz on its ARM Cortex-A5 core. This frequency is achievable under typical thermal and voltage conditions with appropriate DDR memory timing and PLL configuration. The system bus runs up to 166 MHz, and dedicated PLLs support USB HS (480 MHz), audio (11.2896/12.288 MHz), and DDR clocks. ATSAMA5D23B-CN datasheets specify these limits under JEDEC-compliant thermal profiles.

Does the ATSAMA5D23B-CN support dual CAN-FD interfaces?

Yes, the ATSAMA5D23B-CN integrates two fully independent master CAN-FD controllers (CAN0 and CAN1) with SRAM-based mailboxes, time-triggered transmission, and event-triggered operation. This is confirmed in the SAMA5D2 Configuration Summary (DS60001476B-page 5) and distinguishes it from variants like ATSAMA5D27B-CN, which supports only one CAN-FD. ATSAMA5D23B-CN uses dedicated PIO sets for CANRX/CANTX signals with configurable slew rate and drive strength.

What package type and pin count does the ATSAMA5D23B-CN use?

The ATSAMA5D23B-CN is supplied exclusively in a 289-ball LFBGA package (14 × 14 mm body, 0.8 mm ball pitch), as specified in Table 6-1 of DS60001476B. This matches the SAMA5D23 row in the Configuration Summary and is distinct from the 196-ball TFBGA (SAMA5D21) and 256-ball TFBGA (SAMA5D22/27) variants. ATSAMA5D23B-CN pinout follows Table 6-2 and Table 6-3 for variant-specific signal assignments.

How does the ATSAMA5D23B-CN implement hardware-based memory encryption?

The ATSAMA5D23B-CN uses the AESB (AES Bridge) peripheral to perform on-the-fly AES-128/192/256 encryption and decryption of data transferred between the CPU and DDR or QSPI memory. This occurs transparently during read/write cycles without software involvement or performance penalty. ATSAMA5D23B-CN's AESB engine is integrated into the memory controller path and supports key provisioning via secure boot flow and tamper-protected registers.

What low-power modes are supported by the ATSAMA5D23B-CN?

The ATSAMA5D23B-CN supports three software-selectable low-power modes: Idle (CPU halted, peripherals active), Ultra-low-power mode (CPU stopped, peripherals clocked at 512 Hz with SleepWalking™ event response), and Backup mode (RTC + wakeup logic active, DDR in self-refresh). ATSAMA5D23B-CN documentation confirms wakeup from up to nine pins, UART RX, or analog comparator events - with sub-10 µs resume latency in Ultra-low-power mode.