Microchip Technology ATSAMA5D24A-CU
- Part No.:
- ATSAMA5D24A-CU
- Manufacturer:
- Microchip Technology
- Category:
- Microprocessors
- Package:
- 256-TFBGA
- Datasheet:
-
ATSAMA5D24A-CU.pdf
- Description:
- IC MPU SAMA5D2 500MHZ 256TFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ATSAMA5D24A-CU from Microchip Technology is an ultra-low-power Arm Cortex-A5 microprocessor unit (MPU) operating at up to 500 MHz, featuring dual CAN-FD controllers, 10/100 Ethernet MAC with IEEE 1588 PTP support, LCD TFT controller (up to 1280×768), and hardware crypto accelerators (AES-256, SHA-256, TRNG). It integrates 128 KB L2 cache configurable as SRAM, 128 KB scrambled internal SRAM, and supports DDR3L/LPDDR3 memory for industrial HMI and secure IoT gateway applications.
For engineers reviewing the ATSAMA5D24A-CU datasheet, ATSAMA5D24A-CU pinout, ATSAMA5D24A-CU application, or ATSAMA5D24A-CU equivalent, key selection considerations include its dual MCAN controllers (non-ISO CAN FD), extended industrial temperature rating (–40°C to +105°C), TrustZone-enabled secure boot, and 196-ball TFBGA package with 128 I/Os supporting multiplexed FLEXCOM, QSPI, and SDMMC interfaces.
Technical Context
The ATSAMA5D24A-CU implements Armv7-A architecture with NEON SIMD engine and VFPv4 floating-point unit, enabling real-time multimedia processing and deterministic control. Its multilayer bus architecture includes two 16-channel XDMAC controllers and dedicated peripheral DMAs to sustain high-bandwidth transfers across EMAC, USB, ISC, and LCDC without CPU intervention.
Security is enforced via Arm TrustZone partitioning, 5 KB tamper-protected SRAM (1 KB nonerasable), 8 tamper detection pins, on-the-fly AES encryption for DDR/QSPI, and Integrity Check Monitor (ICM) using SHA-256 to validate memory integrity. Low-power operation includes ULP0/ULP1 modes with partial asynchronous wake-up and Backup mode with DDR self-refresh.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-A5 @ 500 MHz with NEON, VFPv4, MMU, and TrustZone |
| Memory Interface | 32-bit DDR3L/LPDDR3 controller supporting up to 512 MB with on-the-fly AESB encryption |
| Peripherals | Dual MCAN (non-ISO CAN FD), 10/100 EMAC with IEEE 1588 PTP, 2×QSPI, 2×SDMMC, 5×FLEXCOM, 12-bit ADC (12 ch) |
| Security | Hardware AES-256/SHA-256/TRNG, 5 KB secure SRAM, 8 tamper pins, ICM, secure bootloader in ROM |
| Package | 196-ball TFBGA, 11×11 mm², 0.75 mm pitch, rated for –40°C to +105°C |
| Power Management | Three low-power modes (Idle, ULP0, Backup); RTC + wake-up logic active in Backup mode with DDR self-refresh |
| I/O Count | 128 fully programmable I/Os with up to 8 peripheral functions per pin and synchronous 32-bit parallel output |
Pinout & Package
ATSAMA5D24A-CU is housed in a 196-ball Thin Fine-Pitch Ball Grid Array (TFBGA) package measuring 11 mm × 11 mm with 0.75 mm ball pitch and 0.75 mm thickness, optimized for industrial thermal and mechanical reliability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PA0–PA31, PB0–PB31, PC0–PC31, PD0–PD31 | Parallel I/O Controller (PIO) | 128 general-purpose or peripheral-multiplexed I/O lines; each supports set/clear register control and synchronous 32-bit write |
| CANRX0/CANTX0, CANRX1/CANTX1 | MCAN Controller Interfaces | Dual independent CAN-FD transceiver interfaces compliant with non-ISO frame format; SRAM-based mailboxes enable time-triggered transmission |
| GTX0–GTX3, GRX0–GRX3, GMDC/GMDIO | GMAC Physical Layer Interface | 10/100 Ethernet MAC signals supporting MII/RMII; integrated IEEE 802.1AS timestamping and credit-based traffic shaping (IEEE 802.1Qav) |
| LCDDAT[23:0], LCDHSYNC, LCDVSYNC, LCDPCK | LCD TFT Controller Outputs | 24-bit RGB parallel interface supporting 1280×768 resolution with hardware overlays, alpha blending, and rotation |
| ISC_D[11:0], ISC_HSYNC, ISC_VSYNC, ISC_PCK | Image Sensor Controller Inputs | 12-bit parallel interface for up to 5 MPixel raw Bayer/YCbCr sensors with ITU-R BT.601/656/1120 compliance |
| QSPI0_IO[0..3], QSPI1_IO[0..3] | Quad SPI Data Lines | Two independent QSPI controllers supporting XIP execution and dual-flash configurations with single/dual/quad I/O modes |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone-enabled Secure Boot | ROM-resident bootloader validates signed firmware images before execution, isolating secure world resources from normal world software |
| Dual MCAN Controllers | Independent SRAM-based mailbox systems with time/event-triggered transmission; supports non-ISO CAN FD frames up to 8 MBps |
| Hardware Crypto Acceleration | Dedicated AES-256/SHA-256/TDES/TRNG engines compliant with FIPS PUB 197/180-2/46-3 and NIST SP 800-22 |
| Low-Power Backup Mode | RTC and wake-up logic remain active while CPU and most peripherals are powered down; DDR retained in self-refresh with <5 µA retention current |
| Configurable L2 Cache/SRAM | 128 KB on-chip memory usable either as L2 cache for Cortex-A5 or as tightly coupled SRAM for deterministic real-time code/data |
| Event System | Hardware event routing between peripherals (e.g., ADC trigger → PWM update) without CPU involvement in Active or Idle modes |
Applications
| Industrial HMI Gateway | Secure Edge IoT Node |
|---|---|
Use Scenario: A factory-floor human-machine interface gateway consolidating data from PLCs, sensors, and barcode scanners while displaying real-time dashboards on a 1024×768 LCD panel. IC Role / Device Role / Timing Role: ATSAMA5D24A-CU serves as the central application processor running Linux, managing dual CAN-FD links to field devices, driving the TFT LCD via 24-bit RGB, and executing encrypted OTA updates. Use Value: Integrated TrustZone and AESB enable secure firmware validation and on-the-fly decryption of display assets stored in QSPI flash, preventing IP theft and unauthorized UI modification. |
Use Scenario: A battery-powered smart meter gateway collecting consumption data via CAN-FD from submeters and transmitting encrypted telemetry over Ethernet AVB to utility cloud infrastructure. IC Role / Device Role / Timing Role: ATSAMA5D24A-CU acts as the secure edge node processor, performing IEEE 1588 timestamping on incoming CAN messages and applying SHA-256 signatures before Ethernet transmission. Use Value: Hardware TRNG and SHA-256 acceleration reduce cryptographic latency by >90% versus software-only implementation, enabling sub-100ms end-to-end signing cycles under RTOS constraints. |
| Medical Imaging Terminal | Ruggedized POS Terminal |
Use Scenario: A portable ultrasound imaging terminal acquiring raw sensor data from a 5 MPixel CMOS image sensor and rendering processed B-mode images on a resistive touchscreen display. IC Role / Device Role / Timing Role: ATSAMA5D24A-CU executes the ISC pipeline for Bayer demosaicing and the LCDC's hardware overlays for UI composition, while the 12-bit ADC reads touchscreen coordinates. Use Value: Dedicated ISC and LCDC hardware offloads >70% of image processing from CPU, enabling 30 fps rendering at 1280×768 with <50 ms system latency. |
Use Scenario: A retail point-of-sale terminal accepting contactless payments via NFC, printing receipts, and logging transactions to e.MMC storage-all within strict PCI PTS v6.0 security requirements. IC Role / Device Role / Timing Role: ATSAMA5D24A-CU hosts the secure payment OS in TrustZone-protected memory, uses tamper-detect pins to invalidate keys upon enclosure breach, and manages dual SDMMC interfaces for transaction logs and firmware updates. Use Value: 8 tamper detection pins and 1 KB nonerasable SRAM ensure immediate cryptographic key erasure on physical intrusion, satisfying PCI PTS tamper-response mandates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Arm Cortex-A5 MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMA5D27A-CU | 289-ball LFBGA package; adds PTC (8×8 capacitive touch), second SDMMC, and environmental monitors (temp/voltage) | Suitable for larger HMI designs requiring multi-touch and dual memory card support; not pin-compatible due to different package and I/O mapping | Select when capacitive touch, extended I/O count, or die-level environmental monitoring are required-requires PCB redesign. |
| i.MX6ULL | Arm Cortex-A7 core @ 900 MHz; single CAN, no TrustZone crypto acceleration; 14x14 mm 289-BGA | Better raw CPU performance but lacks SAMA5D24A-CU's dual CAN-FD, hardware AESB, and tamper protection; targets cost-sensitive Linux gateways without security certification needs | Choose for higher throughput in non-secure embedded Linux applications where CAN FD and cryptographic acceleration are not mandatory. |
Compared with ATSAMA5D24A-CU, ATSAMA5D27A-CU expands touch and monitoring capabilities at the cost of package size and layout compatibility, while i.MX6ULL trades security depth and dual CAN-FD for higher clock speed and broader ecosystem support-neither offers drop-in replacement capability.
Availability
ATSAMA5D24A-CU is available at Aetrix Electronics and suitable for industrial HMI gateways, secure edge IoT nodes, medical imaging terminals, and ruggedized POS terminals requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for ATSAMA5D24A-CU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a leading provider of microcontrollers, analog components, and Flash-IP solutions, delivering secure, low-power, and highly integrated semiconductor products for industrial, automotive, and IoT markets.
The SAMA5D2 product line was designed specifically for secure, ultra-low-power embedded applications demanding Arm Cortex-A performance with hardware-enforced trust, including industrial HMIs, medical edge devices, and certified payment terminals.
FAQ
What is the maximum operating temperature range for the ATSAMA5D24A-CU?
The ATSAMA5D24A-CU is qualified for extended industrial temperature operation from –40°C to +105°C ambient, verified per Microchip's qualification standards and supported by thermal design guidelines in the DS60001476H datasheet. This rating applies specifically to the 196-ball TFBGA variant and enables deployment in harsh environments such as factory automation cabinets and outdoor kiosks without derating.
Does the ATSAMA5D24A-CU support ISO-compliant CAN FD?
No-the ATSAMA5D24A-CU implements MCAN controllers using the non-ISO CAN FD frame format and does not pass the ISO 16845-1:2016 conformance test. It supports CAN FD data rates up to 8 Mbps and features SRAM-based mailboxes with time-triggered transmission, but interoperability with ISO-standard CAN FD networks requires protocol translation or external transceivers.
How is secure boot implemented on the ATSAMA5D24A-CU?
The ATSAMA5D24A-CU executes a ROM-resident secure bootloader that validates digital signatures of first-stage firmware using RSA-2048 or ECDSA-256 before loading into internal SRAM. The process enforces TrustZone isolation, disables debug interfaces upon failure, and leverages the 64-bit SAIC to prevent privilege escalation-details are specified in the SAMA5D2 Series Secure Boot Strategy document under NDA.
Which power management ICs are recommended for the ATSAMA5D24A-CU?
Microchip recommends the MCP16501A and MCP16502AA PMICs for ATSAMA5D24A-CU designs. Both provide pin-selectable VDDIODDR (1.2 V / 1.35 V / 1.8 V) to match DDR3L/LPDDR3 memory, leakage-free I²C control in Backup mode, and dedicated rails for VDDCORE, VDDIOP, and VDDFUSE. The MCP16502AA adds a fourth buck regulator for auxiliary loads.
Can the ATSAMA5D24A-CU's L2 cache be used as general-purpose SRAM?
Yes-the ATSAMA5D24A-CU's 128 KB L2 cache is configurable via the L2CC register to operate either as cache for the Cortex-A5 core or as tightly coupled SRAM. When configured as SRAM, it provides deterministic zero-wait-state access for real-time tasks such as interrupt service routines or safety-critical buffers, with full ECC protection enabled.
ATSAMA5D24A-CU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- 256-TFBGA
- Series:
- SAMA5D2
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- ARM® Cortex®-A5
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 500MHz
- Co-Processors/DSP:
- Multimedia; NEON™ MPE
- RAM Controllers:
- LPDDR1, LPDDR2, LPDDR3, DDR2, DDR3, DDR3L, QSPI
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- Keyboard, LCD, Touchscreen
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 + HSIC
- Voltage - I/O:
- 3.3V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ, Boot Security, Cryptography, RTIC, Secure Fusebox, Secure JTAG, Secure Memory, Secure RTC
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 256-TFBGA (8x8)
- Additional Interfaces:
- I2C, SMC, SPI, UART, USART, QSPI
ATSAMA5D24A-CU FAQ
1.How can I place an order for ATSAMA5D24A-CU through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMA5D24A-CU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMA5D24A-CU reliable?
The price and inventory of ATSAMA5D24A-CU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMA5D24A-CU is usually 5 days.
3.What payment methods are accepted for ATSAMA5D24A-CU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMA5D24A-CU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMA5D24A-CU?
ATSAMA5D24A-CU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMA5D24A-CU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMA5D24A-CU?
For technical support, including ATSAMA5D24A-CU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMA5D24A-CU requirements.
6.How does Aetrix verify that ATSAMA5D24A-CU is sourced from the original manufacturer or authorized distributors?
All ATSAMA5D24A-CU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMA5D24A-CU meets industry standards.
7.What is the process for return or replacement of ATSAMA5D24A-CU?
All ATSAMA5D24A-CU units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMA5D24A-CU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMA5D24A-CU part is unused and in its original packaging.
Return procedure for ATSAMA5D24A-CU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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