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Microchip Technology ATSAMA5D24B-CUR
- Part No.:
- ATSAMA5D24B-CUR
- Manufacturer:
- Microchip Technology
- Category:
- Microprocessors
- Package:
- 256-TFBGA
- Datasheet:
-
ATSAMA5D24B-CUR.pdf
- Description:
- IC MPU SAMA5D2 500MHZ 256TFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:2,402
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Product details
Overview
ATSAMA5D24B-CUR from Microchip Technology is an ultra-low-power Arm Cortex-A5-based microprocessor unit (MPU) operating at up to 500 MHz, integrating a 128-Kbyte configurable L2 cache, dual CAN-FD controllers, 10/100 Ethernet MAC with IEEE 1588 PTP support, and hardware crypto accelerators (AES-256, SHA-256, TRNG). It supports DDR2/DDR3L/LPDDR2/LPDDR3 memory, QSPI, e.MMC, and NAND Flash, and targets secure industrial HMI, IoT gateways, and point-of-sale terminals.
For engineers reviewing the ATSAMA5D24B-CUR datasheet, ATSAMA5D24B-CUR pinout, ATSAMA5D24B-CUR application, or ATSAMA5D24B-CUR equivalent, this page delivers verified technical context, validated package mapping, confirmed peripheral capabilities (including dual MCAN, LCDC, ISC, and secure boot), and real-world selection guidance for industrial embedded designs requiring extended temperature operation (-40°C to +105°C) and Arm TrustZone®-enabled security.
Technical Context
The ATSAMA5D24B-CUR implements an Armv7-A architecture Cortex-A5 core with NEON SIMD engine, MMU, and floating-point unit, enabling Linux® execution and high-precision signal processing. Its multilayer bus architecture integrates two 16-channel DMA controllers and dedicated peripheral DMAs to sustain concurrent high-bandwidth transfers across EMAC, USB, QSPI, and SDMMC without CPU overhead.
Security is enforced via Arm TrustZone®, on-the-fly AES encryption/decryption for DDR and QSPI, 5-Kbyte scrambled SRAM with tamper response, Integrity Check Monitor (ICM) using SHA-256, and a secure bootloader in 64-Kbyte scrambled ROM. Low-power operation includes three software-selectable modes: Idle, Ultra-Low-Power (ULP0/ULP1), and Backup-with DDR self-refresh support and RTC persistence.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-A5 @ up to 500 MHz with NEON, FPU, MMU, and TrustZone®-enables full Linux OS and real-time deterministic tasks. |
| Memory Interface | 32-bit DDR2/DDR3L/LPDDR2/LPDDR3 controller supporting up to 512 Mbytes; includes on-the-fly AES encryption/decryption path. |
| Peripherals | Dual host CAN-FD (MCAN) controllers with SRAM mailboxes; 10/100 EMAC with IEEE 1588 PTP, AVB, and 802.1Qav hardware shaping. |
| Security | Hardware AES-256/192/128, SHA-1/224/256/384/512, TDES, TRNG compliant with FIPS PUBs 140-3 and 197; 5-Kbyte tamper-responsive SRAM. |
| Package & Temp | 256-ball TFBGA, 8×8 mm², 0.4 mm pitch; qualified for industrial temperature range (-40°C to +105°C). |
| Low-Power Modes | Ultra-Low-Power mode with fast wake-up; Backup mode with RTC active and optional DDR self-refresh; wake-up from 9 pins, UART, or analog comparator. |
| I/O Count | 105 programmable I/O lines with up to eight peripheral functions per pin and synchronous 32-bit parallel output capability. |
Pinout & Package
ATSAMA5D24B-CUR is housed in a 256-ball Thin Fine-Pitch Ball Grid Array (TFBGA) package measuring 8 mm × 8 mm with 0.4 mm ball pitch and 1.05 mm thickness. This package supports high-density routing and thermal performance suitable for industrial edge applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| XIN / XOUT | Main crystal oscillator input/output | Supports 8–24 MHz external crystal; required for system clock generation and PLL reference. |
| XIN32 / XOUT32 | 32.768 kHz slow clock oscillator input/output | Feeds secure RTC and low-power backup domain; enables timekeeping during ULP/Backup modes. |
| NRST | Active-low microprocessor reset | Asynchronous global reset input; initiates cold boot and clears internal state including security registers. |
| SHDN | Shutdown control output | Drives external PMIC (e.g., MCP16502) to enter BSR (Backup Self-Refresh) mode; coordinated with PIOBU0 for entry/exit. |
| PIOBU0–PIOBU7 | Tamper/wake-up inputs | Eight dedicated pins for static/dynamic intrusion detection or asynchronous wake-up events in low-power states. |
| DDR_D[31:0] / DDR_A[13:0] | DDR data/address bus | 32-bit bidirectional data and 14-bit address interface for DDR2/DDR3L/LPDDR2/LPDDR3 memory subsystem. |
| GTX0–GTX3 / GRX0–GRX3 | EMAC transmit/receive data | 4-bit nibble-wide RMII/MII interface supporting 10/100 Mbps Ethernet with IEEE 1588 timestamping. |
| CANRX0/CANTX0, CANRX1/CANTX1 | CAN-FD receive/transmit | Dual independent MCAN interfaces implementing non-ISO CAN FD frame format; no ISO 16845-1 conformance. |
Key Features
| Feature | Design Value |
|---|---|
| Arm TrustZone®-enabled secure world isolation | Hardware-enforced separation of secure/non-secure code and data; protects bootloader, keys, and encrypted firmware execution. |
| Configurable 128-Kbyte L2 cache or SRAM | Runtime reconfiguration allows use as high-speed cache or tightly coupled memory for latency-critical real-time tasks. |
| On-the-fly AES encryption/decryption (AESB) | Transparent encryption of DDR and QSPI memory accesses-no software overhead, no performance penalty for secure storage. |
| Event System for autonomous peripheral interaction | Enables peripherals (e.g., ADC, PWM, TC) to trigger actions without CPU involvement-reduces power and latency in Active/Idle modes. |
| Secure Bootloader in 64-Kbyte scrambled ROM | Immutable first-stage boot code verifies signature and integrity of second-stage firmware before execution-prevents unauthorized code injection. |
| Integrated Integrity Check Monitor (ICM) | SHA-256-based runtime memory verification detects unauthorized modification of critical code/data regions-including external flash. |
Applications
| Industrial HMI Terminal | Secure IoT Gateway |
|---|---|
|
Use Scenario: Touch-enabled factory floor display with real-time sensor visualization and remote diagnostics over cellular/Wi-Fi. IC Role / Device Role / Timing Role: Main application processor running Linux with QT-based UI; LCDC drives 1024×768 RGB panel; ISC interfaces 5-Mpixel camera for QR/barcode scanning. Use Value: Dual CAN-FD enables direct PLC communication; hardware crypto accelerators offload TLS/DTLS for secure cloud connectivity without CPU saturation. |
Use Scenario: Edge gateway aggregating Modbus RTU, CAN bus, and BLE sensor data for protocol translation and local AI inference. IC Role / Device Role / Timing Role: Central MPU executing containerized services; dual MCAN handles legacy industrial networks; EMAC + USB host supports wired/wireless uplinks. Use Value: TrustZone® isolates secure firmware update service; AESB encrypts local e.MMC storage; 105°C rating ensures reliability in uncooled enclosures. |
| Point-of-Sale (POS) Terminal | Medical Data Logger |
|
Use Scenario: PCI-compliant payment terminal with contactless card reader, thermal printer, and biometric authentication. IC Role / Device Role / Timing Role: Secure application processor managing EMV L2 kernel; PTC provides capacitive touch for PIN entry; TRNG seeds cryptographic operations. Use Value: Tamper-detect SRAM erases keys on physical intrusion; ICM validates bootloader and payment app integrity at every boot. |
Use Scenario: Battery-powered wearable device logging ECG, temperature, and motion data with encrypted local storage and periodic BLE sync. IC Role / Device Role / Timing Role: Low-power MPU in Backup mode with RTC and ADC sampling; wakeup triggered by analog comparator threshold crossing. Use Value: ULP1 mode draws sub-100 µA while retaining RTC and wake logic; AES-256 encrypts stored patient data before writing to QSPI flash. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Arm Cortex-A5 MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMA5D27B-CUR | 289-ball LFBGA, 128 I/Os, dual CAN-FD, 10/100 EMAC, same core/peripherals but higher I/O count and larger package. | Preferred for designs requiring >105 I/Os or additional LCD overlays; not pin-compatible due to different ball count and layout. | Select when board layout accommodates 14×14 mm LFBGA and system demands expanded peripheral multiplexing or larger DDR bandwidth. |
| i.MX6ULL | Arm Cortex-A7 @ 900 MHz, single-core, no TrustZone®-enabled secure world, no on-the-fly memory encryption, different crypto block (CAAM vs. SAMA5D2's AESB/ICM). | Better suited for cost-sensitive Linux applications without stringent security certification requirements (e.g., basic gateways, displays). | Choose only if security compliance (IEC 60730 Class B, FIPS) is not required and existing i.MX6ULL toolchain familiarity outweighs SAMA5D2's tamper resilience. |
Compared with ATSAMA5D24B-CUR, ATSAMA5D27B-CUR offers more I/Os and larger memory bandwidth in a physically incompatible package, while i.MX6ULL trades hardware-enforced security and ultra-low-power modes for higher raw CPU frequency and broader ecosystem support-making it unsuitable for certified secure or battery-backed industrial deployments.
Availability
ATSAMA5D24B-CUR is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, and medical data loggers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for safety-critical production.
Supply support for ATSAMA5D24B-CUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a leading provider of microcontrollers, analog components, and Flash-IP solutions, emphasizing security, reliability, and long-term product availability for industrial and automotive markets.
The SAMA5D2 series was designed specifically for secure, ultra-low-power embedded applications demanding Arm TrustZone®, hardware crypto acceleration, and industrial temperature resilience-targeting POS, smart energy, and industrial automation systems.
FAQ
What is the maximum operating frequency of the ATSAMA5D24B-CUR?
The ATSAMA5D24B-CUR operates at up to 500 MHz on its Arm Cortex-A5 core. This frequency is achievable under typical conditions with appropriate voltage scaling and thermal management. The device also features a 600–1200 MHz system PLL and a dedicated 480 MHz USB PLL, both independently configurable. All timing specifications in the official DS60001476H datasheet assume operation within the rated industrial temperature range (-40°C to +105°C) and specified VDDCORE/VDDIO supply conditions.
Does the ATSAMA5D24B-CUR support CAN FD, and is it ISO 16845-1 compliant?
The ATSAMA5D24B-CUR integrates two host CAN-FD (MCAN) controllers that implement the non-ISO CAN FD frame format. As explicitly stated in the official datasheet, these controllers do not pass the CAN FD Conformance Test per ISO 16845-1:2016. Therefore, ATSAMA5D24B-CUR is suitable for proprietary or non-certified CAN FD networks but not for applications requiring formal ISO 16845-1 validation-such as certain automotive or safety-critical industrial protocols.
Which memory types does the ATSAMA5D24B-CUR support natively?
The ATSAMA5D24B-CUR natively supports DDR2, DDR3L, LPDDR1, LPDDR2, and LPDDR3 via its 32-bit DDR controller; QSPI flash through two dedicated QSPI interfaces; e.MMC 4.51 and SD 3.0 via SDMMC0; and SLC/MLC NAND Flash with up to 32-bit BCH ECC via its integrated NAND controller. It does not support DDR4 or GDDR memory types. Memory configuration-including DLL-on/off settings for DDR3L-is controlled via register programming and validated in the DS60001476H datasheet.
How does the ATSAMA5D24B-CUR implement hardware security for firmware integrity?
The ATSAMA5D24B-CUR uses its Integrity Check Monitor (ICM) peripheral to perform SHA-256 hashing of designated memory regions-including internal ROM, external QSPI, and DDR-and compare results against stored signatures. This occurs autonomously at boot and optionally during runtime. Combined with the 64-Kbyte scrambled ROM containing the secure bootloader and tamper-erased SRAM, ATSAMA5D24B-CUR enforces end-to-end firmware authenticity and resistance to replay or modification attacks.
What power management ICs are recommended for the ATSAMA5D24B-CUR?
Microchip recommends the MCP16502AA and MCP16501A PMICs for ATSAMA5D24B-CUR. Both provide leakage-free interface support across all power modes-including Backup-and feature pin-selectable VDDIODDR outputs (1.2 V, 1.35 V, or 1.8 V) to match DDR3L, LPDDR2, or DDR2 memory requirements. The MCP16502AA supports four DC-DC rails and two LDOs in a 4×4 mm QFN, while the MCP16501A offers three DC-DC rails and one LDO in a space-constrained 4×4 mm QFN24 package.
ATSAMA5D24B-CUR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- 256-TFBGA
- Series:
- SAMA5D2
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Core Processor:
- ARM® Cortex®-A5
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 500MHz
- Co-Processors/DSP:
- Multimedia; NEON™ MPE
- RAM Controllers:
- LPDDR1, LPDDR2, LPDDR3, DDR2, DDR3, DDR3L, QSPI
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- Keyboard, LCD, Touchscreen
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 + HSIC
- Voltage - I/O:
- 3.3V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ, Boot Security, Cryptography, RTIC, Secure Fusebox, Secure JTAG, Secure Memory, Secure RTC
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 256-TFBGA (8x8)
- Additional Interfaces:
- I2C, SMC, SPI, UART, USART, QSPI
ATSAMA5D24B-CUR FAQ
1.How can I place an order for ATSAMA5D24B-CUR through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMA5D24B-CUR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMA5D24B-CUR reliable?
The price and inventory of ATSAMA5D24B-CUR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMA5D24B-CUR is usually 5 days.
3.What payment methods are accepted for ATSAMA5D24B-CUR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMA5D24B-CUR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMA5D24B-CUR?
ATSAMA5D24B-CUR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMA5D24B-CUR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMA5D24B-CUR?
For technical support, including ATSAMA5D24B-CUR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMA5D24B-CUR requirements.
6.How does Aetrix verify that ATSAMA5D24B-CUR is sourced from the original manufacturer or authorized distributors?
All ATSAMA5D24B-CUR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMA5D24B-CUR meets industry standards.
7.What is the process for return or replacement of ATSAMA5D24B-CUR?
All ATSAMA5D24B-CUR units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMA5D24B-CUR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMA5D24B-CUR part is unused and in its original packaging.
Return procedure for ATSAMA5D24B-CUR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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