Microchip Technology ATSAMA5D24C-CUR

Overview

ATSAMA5D24C-CUR from Microchip Technology is an ultra-low-power Arm Cortex-A5-based microprocessor unit (MPU) operating at up to 500 MHz, featuring dual CAN-FD controllers, 10/100 Ethernet MAC with IEEE 802.1AS timestamping, and hardware crypto acceleration (AES-256, SHA-512, TRNG). It integrates a 12-channel 12-bit ADC with resistive touchscreen support and is qualified for industrial temperature range (−40°C to +105°C).

For engineers reviewing the ATSAMA5D24C-CUR datasheet, ATSAMA5D24C-CUR pinout, ATSAMA5D24C-CUR application, or ATSAMA5D24C-CUR equivalent, this page delivers verified technical context, validated package mapping (256-ball TFBGA, 8×8 mm, 0.4 mm pitch), confirmed low-power modes (ULP0/ULP1/Backup), real-world security features (TrustZone, tamper detection, on-the-fly DDR encryption), and precise peripheral allocation per SAMA5D24 variant.

Technical Context

The ATSAMA5D24C-CUR implements a full Armv7-A architecture with MMU, NEON SIMD engine, and floating-point unit (FPU), enabling Linux® execution and high-precision signal processing. Its memory subsystem includes 32-KB L1 instruction/data caches, configurable 128-KB L2 cache (usable as SRAM), and a high-bandwidth 32-bit DDR controller supporting DDR3L/LPDDR2/LPDDR3 with on-the-fly AESB encryption.

It features two MCAN controllers compliant with non-ISO CAN FD frame format (not ISO 16845-1:2016 conformant), a 10/100 GMAC with IEEE 802.1Qav traffic shaping and PTP hardware timestamping, and a dedicated 128-KB scrambled internal SRAM for secure boot and runtime isolation. The device supports three software-selectable low-power modes - Idle, Ultra-Low-Power (ULP0/ULP1), and Backup - with partial asynchronous wake-up via up to nine pins or UART reception.

Key Specifications

Pinout & Package

ATSAMA5D24C-CUR is housed in a 256-ball Thin Fine-Pitch Ball Grid Array (TFBGA) package measuring 8 mm × 8 mm with 0.4 mm ball pitch and 1.05 mm thickness. This package supports 128 I/Os with up to eight peripheral functions multiplexed per pin, including dedicated tamper/wake-up pins (PIOBU0–PIOBU7), DDR interface signals (DDR_D[31:0], DDR_A[13:0], DDR_CK/CLKN), and dual CAN transceiver interfaces (CANRX0/CANTX0, CANRX1/CANTX1).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-performance, secure MPU applications.

Compared with ATSAMA5D24C-CUR, ATSAMA5D27C-CUR adds environmental sensing and die shielding at the cost of larger LFBGA packaging, while ATSAMA5D22C-CUR reduces peripheral count and eliminates second CAN to lower BOM cost - both require PCB redesign and firmware adaptation.

Availability

ATSAMA5D24C-CUR is available at Aetrix Electronics and suitable for industrial HMI panels, secure IoT gateways, medical point-of-care devices, and railway signaling controllers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for ATSAMA5D24C-CUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and Flash-IP solutions, with global design, manufacturing, and support infrastructure serving industrial, automotive, and communications markets.

The SAMA5D2 series was designed as a secure, ultra-low-power Arm Cortex-A5 MPU family targeting Linux-capable edge devices requiring hardware-enforced trust, deterministic networking, and extended temperature operation - ATSAMA5D24C-CUR specifically delivers dual CAN-FD and industrial-grade reliability in compact TFBGA packaging.

FAQ

What is the maximum operating frequency of the ATSAMA5D24C-CUR?

The ATSAMA5D24C-CUR operates at up to 500 MHz on its Arm Cortex-A5 core. This frequency is sustained under typical industrial conditions with appropriate power delivery and thermal management. The device also includes a 166 MHz system bus and dedicated PLLs for USB (480 MHz) and audio (11.2896/12.288 MHz), all independently configurable. ATSAMA5D24C-CUR maintains this performance across its −40°C to +105°C qualification range.

Does the ATSAMA5D24C-CUR support ISO 16845-1:2016 CAN FD conformance testing?

No, the ATSAMA5D24C-CUR implements MCAN controllers using the non-ISO CAN FD frame format and does not pass the CAN FD Conformance Test per ISO 16845-1:2016. Its MCAN modules support flexible data-rate messaging up to 5 Mbps but lack full ISO standard compliance. ATSAMA5D24C-CUR remains suitable for proprietary or vendor-specific CAN FD networks where frame format compatibility is controlled within the system design.

Which package type is used by the ATSAMA5D24C-CUR?

The ATSAMA5D24C-CUR uses a 256-ball Thin Fine-Pitch Ball Grid Array (TFBGA) package measuring 8 mm × 8 mm with 0.4 mm ball pitch and 1.05 mm thickness. This matches the SAMA5D24 variant's specified packaging and supports 128 I/Os with eight-function multiplexing. ATSAMA5D24C-CUR is not pin-compatible with the 196-ball or 289-ball variants of the SAMA5D2 series.

What security features are implemented in hardware on the ATSAMA5D24C-CUR?

The ATSAMA5D24C-CUR integrates TrustZone, 5 KB of tamper-responsive scrambled SRAM (1 KB nonerasable), eight dedicated tamper pins (PIOBU0–PIOBU7), Integrity Check Monitor (ICM) with SHA-256, on-the-fly AESB encryption for DDR/QSPI, and hardware crypto engines for AES-256, SHA-512, TDES, and NIST-compliant TRNG. These features enable secure boot, encrypted code execution, and runtime memory integrity verification - all without software overhead. ATSAMA5D24C-CUR leverages these to meet IEC 60730 Class B safety requirements.

Can the ATSAMA5D24C-CUR execute Linux from encrypted external memory?

Yes, the ATSAMA5D24C-CUR supports on-the-fly AESB encryption/decryption for both DDR and QSPI memories, enabling direct execution of encrypted Linux kernel and root filesystem from external storage without CPU-side decryption. This capability is implemented in hardware and transparent to the OS, preserving performance while ensuring code confidentiality. ATSAMA5D24C-CUR uses dedicated key storage and scrambling logic to protect encryption keys during boot and runtime.