Microchip Technology ATSAMA5D26A-CUR
- Part No.:
- ATSAMA5D26A-CUR
- Manufacturer:
- Microchip Technology
- Category:
- Microprocessors
- Package:
- 289-LFBGA
- Datasheet:
-
ATSAMA5D26A-CUR.pdf
- Description:
- IC MPU SAMA5D2 500MHZ 289LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,325
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Product details
Overview
ATSAMA5D26A-CUR from Microchip Technology is an ultra-low-power Arm Cortex-A5-based microprocessor unit (MPU) operating at up to 500 MHz, featuring dual CAN-FD controllers, 10/100 Ethernet MAC with AVB and IEEE 1588 support, LCD TFT controller (1024×768), and hardware crypto accelerators (AES-256, SHA-256, TRNG). It integrates 128 KB L2 cache configurable as SRAM, 128 KB scrambled internal SRAM, and supports DDR3L/LPDDR3 memory for industrial HMI and secure IoT gateway applications.
For engineers reviewing the ATSAMA5D26A-CUR datasheet, ATSAMA5D26A-CUR pinout, ATSAMA5D26A-CUR application, or ATSAMA5D26A-CUR equivalent, key selection considerations include its dual MCAN controllers (non-ISO CAN FD), extended industrial temperature rating (−40°C to +105°C), TrustZone-enabled secure boot, on-the-fly AES encryption for DDR/QSPI, and 12-channel 12-bit ADC with resistive touchscreen support.
Technical Context
The ATSAMA5D26A-CUR implements a dual-bus H64MX/H32MX peripheral architecture with two 16-channel XDMAC controllers, enabling zero-overhead data movement between peripherals like GMAC, USB, ISC, and SDMMC. Its security subsystem includes a dedicated Secured Advanced Interrupt Controller (SAIC), Integrity Check Monitor (ICM) with SHA-256, tamper-detection circuitry across eight PIOBU pins, and 5 KB of secure SRAM with erasable/non-erasable segments.
Power management features three software-selectable low-power modes: Idle (CPU halted, peripherals active), Ultra-Low-Power (ULP0/ULP1 with sub-1 kHz clocking and partial wake-up), and Backup mode with RTC and DDR self-refresh. The device uses a 12 MHz RC oscillator and supports external 8–24 MHz crystal or 32.768 kHz slow clock, with PLLs generating system (600–1200 MHz), USB (480 MHz), and audio (11.2896/12.288 MHz) clocks.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-A5, Armv7-A architecture, NEON SIMD, FPU, up to 500 MHz - enables Linux execution and real-time signal processing in resource-constrained edge devices. |
| Memory Interface | 32-bit DDR3L/LPDDR3 controller supporting up to 512 MB with on-the-fly AES encryption - allows secure, high-bandwidth external memory access without software overhead. |
| Security Acceleration | AES-128/192/256, SHA-1/224/256/384/512, TDES, TRNG compliant with FIPS PUB 140-3 - offloads cryptographic operations from CPU, enabling TLS/IPsec at line rate in gateways. |
| Connectivity Peripherals | Dual MCAN controllers (SRAM mailboxes, time-triggered transmission), 10/100 EMAC with IEEE 1588 PTP and AVB hardware timestamping - supports deterministic industrial networking and automotive diagnostics. |
| User Interface Support | 24-bit RGB LCD controller (1024×768), Image Sensor Controller (ISC) for 5 MPixel sensors, 8×8 capacitive touch (PTC), 12-bit ADC with touchscreen - enables rich HMI in medical panels and smart building terminals. |
| Package & Temperature | 289-ball LFBGA (14×14 mm, 0.8 mm pitch), rated for −40°C to +105°C ambient - suitable for convection-cooled industrial control cabinets and outdoor edge nodes. |
| Power Management | Ultra-Low-Power mode with fast wake-up (<10 µs), Backup mode with 5 KB SRAM retention and DDR self-refresh - extends battery life in always-on monitoring systems with infrequent sensor polling. |
Pinout & Package
ATSAMA5D26A-CUR is housed in a 289-ball Low-Profile Fine-Pitch Ball Grid Array (LFBGA) package measuring 14 mm × 14 mm with 0.8 mm ball pitch and 1.4 mm thickness. This package supports high I/O density (up to 128 programmable PIOs) and thermal performance required for sustained 500 MHz operation in industrial environments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| NRST | Active-low reset input | Asynchronous processor reset; must be held low ≥100 ns for reliable initialization; compatible with standard push-button or supervisor IC reset circuits. |
| DDR_D[31:0] | DDR3L/LPDDR3 bidirectional data bus | 32-bit wide interface supporting burst transfers at up to 533 MT/s; requires matched trace lengths and on-die termination calibration via DDR_CAL pin. |
| CANRX0/CANTX0 CANRX1/CANTX1 | Dual CAN-FD receive/transmit pairs | Hardware-isolated differential signaling paths; each pair supports non-ISO CAN FD frames up to 5 Mbps; no external transceivers required for logic-level connection. |
| GMAC_GTX0–GTX3 GMAC_GRX0–GRX3 | Ethernet 10/100 transmit/receive data | 4-bit nibble-mode MII interface; requires external PHY; GREFCK input enables precise clock synchronization for IEEE 1588 timestamping. |
| LCDDAT[23:0] | LCD RGB data bus | 24-bit parallel output driving TFT panels at pixel clocks up to 85 MHz; supports alpha blending and hardware overlays for multi-layer UI composition. |
| PTC_X[7:0]/PTC_Y[7:0] | Capacitive touch controller lines | 8×8 matrix scan interface; integrated charge-transfer measurement eliminates need for external touch controller IC in HMI designs. |
Key Features
| Feature | Design Value |
|---|---|
| Arm TrustZone security partitioning | Hardware-enforced isolation between secure world (bootloader, crypto keys, firmware updates) and normal world (Linux OS, applications), preventing privilege escalation attacks. |
| On-the-fly AESB memory encryption | Real-time decryption of code/data fetched from QSPI or DDR memory using keys stored only in secure SRAM - prevents firmware extraction via flash dumping. |
| Dual MCAN with time-triggered transmission | Independent SRAM mailboxes per CAN controller enable deterministic scheduling of messages without CPU intervention - critical for functional safety in vehicle ECUs. |
| Event System for peripheral autonomy | Allows peripherals (e.g., ADC, timers, UART) to trigger actions (DMA transfers, PWM updates) without CPU involvement - reduces latency and power in sensor fusion applications. |
| Scrambled 128 KB internal SRAM | Memory content obfuscated using hardware-generated keys; inaccessible when powered down - protects runtime secrets like session keys and biometric templates. |
| Integrity Check Monitor (ICM) | SHA-256 hashing engine that continuously verifies integrity of external memories (QSPI, DDR); generates interrupt on tampering detection - essential for IEC 60730 Class B compliance. |
Applications
| Industrial HMI Terminal | Secure IoT Gateway |
|---|---|
Use Scenario: A wall-mounted panel in factory automation displaying real-time machine status, alarms, and configuration menus with glove-compatible touch. IC Role / Device Role / Timing Role: Main application processor executing Linux Qt GUI, driving 1024×768 RGB display via LCDC, sampling 8-channel analog inputs via ADC, and communicating over dual CAN to PLCs. Use Value: Integrated PTC and resistive touchscreen ADC eliminate external touch controller; TrustZone isolates HMI software from secure firmware update logic; ULP mode extends backup battery life during power outages. |
Use Scenario: Edge gateway aggregating Modbus RTU, CAN bus, and BLE sensor data, then forwarding encrypted telemetry to cloud via TLS over Ethernet. IC Role / Device Role / Timing Role: Secure network host running embedded Linux, performing AES-256 encryption/decryption in hardware, managing time-synchronized packet routing via IEEE 1588 PTP, and validating firmware signatures using ICM. Use Value: On-the-fly AESB encrypts OTA firmware images stored in QSPI; dual MCAN interfaces connect legacy industrial networks; hardware crypto accelerators sustain 20+ concurrent TLS sessions without CPU saturation. |
| Medical Diagnostic Device | Smart Building Controller |
Use Scenario: Portable ultrasound or ECG analyzer requiring FDA-compliant secure boot, tamper-evident logging, and real-time image processing. IC Role / Device Role / Timing Role: Real-time imaging processor using NEON for FFT-based signal analysis, ISC for raw sensor capture, and secure bootloader verifying signed DICOM image pipelines. Use Value: 8 tamper-detection pins (PIOBU) detect physical intrusion; 5 KB secure SRAM stores cryptographic keys and audit logs; IEC 60730 Class B-certified clock monitoring ensures safe operation during diagnostic cycles. |
Use Scenario: HVAC and lighting controller deployed in commercial buildings, integrating BACnet MS/TP, KNX, and wireless Zigbee modules via serial interfaces. IC Role / Device Role / Timing Role: Central protocol translator using five FLEXCOMs (USART/SPI/TWI) to bridge field buses, managing schedule-based HVAC control via RTC and PWM-driven valve actuators. Use Value: Five UARTs and dual QSPI interfaces enable simultaneous connectivity to legacy BACnet MSTP, modern wireless SoCs, and local eMMC storage; Backup mode retains schedules during AC loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMA5D27A-CUR | Same 289-ball LFBGA package but adds environmental monitors (temperature/voltage/frequency) and die shield; supports extended tamper detection with dynamic PIOBU. | Required for applications needing NDA-covered environmental monitoring (e.g., payment terminals, defense comms) where SAMA5D26 lacks die-level anomaly detection. | Select ATSAMA5D27A-CUR when tamper response must include voltage/frequency deviation alerts beyond static pin detection. |
| i.MX6ULL | ARM Cortex-A7 core (up to 900 MHz), single CAN, no TrustZone memory protection, no on-the-fly memory encryption, different pinout and memory controller. | Suitable for cost-sensitive Linux gateways without stringent security requirements; lacks hardware-accelerated crypto and secure boot enforcement of SAMA5D26. | Choose i.MX6ULL only if design already uses its ecosystem and security compliance (FIPS, IEC 60730) is not mandated. |
Compared with ATSAMA5D27A-CUR, ATSAMA5D26A-CUR omits environmental monitors but maintains identical CAN/Ethernet/USB feature set and industrial temperature rating; versus i.MX6ULL, it delivers stronger hardware-rooted security and deterministic dual-CAN timing at lower peak frequency - making it preferable for certified industrial and medical edge devices.
Availability
ATSAMA5D26A-CUR is available at Aetrix Electronics and suitable for industrial HMI terminals, secure IoT gateways, and medical diagnostic devices requiring stable component supply, long-term lifecycle assurance, and qualified extended-temperature operation.
Supply support for ATSAMA5D26A-CUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company delivering microcontrollers, analog, FPGA, and security solutions with emphasis on reliability, longevity, and embedded system integration.
The SAMA5D2 product line was designed specifically for secure, ultra-low-power Linux-capable edge devices in industrial automation, healthcare, and smart infrastructure - combining Arm Cortex-A performance with hardware-enforced trust and deterministic real-time peripherals.
FAQ
What is the maximum DDR3L memory capacity supported by ATSAMA5D26A-CUR?
The ATSAMA5D26A-CUR supports up to 512 Mbytes of DDR3L memory via its 32-bit wide, high-bandwidth DDR controller. This capacity is achieved using 8-bank configurations with DLL-off operation, and includes hardware ECC and on-the-fly AES encryption/decryption for secure data handling in ATSAMA5D26A-CUR-based systems.
Does ATSAMA5D26A-CUR support ISO 16845-1:2016 CAN FD conformance testing?
No, ATSAMA5D26A-CUR implements the non-ISO CAN FD frame format and does not pass the CAN FD Conformance Test according to ISO 16845-1:2016. Its dual MCAN controllers are optimized for time-triggered and event-triggered communication in industrial networks rather than automotive ISO-compliant FD deployment.
How is secure boot implemented in ATSAMA5D26A-CUR?
ATSAMA5D26A-CUR implements secure boot using a 64-Kbyte scrambled and maskable ROM containing a secure bootloader, verified against cryptographic signatures stored in fuses. Boot flow enforces TrustZone isolation, checks image integrity via ICM, and loads only authenticated code into secure SRAM before handing control to the normal world - all enforced in hardware within ATSAMA5D26A-CUR.
What power management modes are available on ATSAMA5D26A-CUR?
ATSAMA5D26A-CUR offers three software-selectable low-power modes: Idle (CPU halted, peripherals active), Ultra-Low-Power (ULP0/ULP1 with sub-1 kHz clocking and partial wake-up), and Backup mode with RTC and DDR self-refresh. Wake-up sources include up to nine PIO pins, UART reception, and analog comparator events - enabling flexible energy optimization in ATSAMA5D26A-CUR deployments.
Which external PMICs are recommended for ATSAMA5D26A-CUR?
Microchip recommends the MCP16502AA and MCP16501A PMICs for ATSAMA5D26A-CUR. Both provide leakage-free interface support across all power modes, pin-selectable VDDIODDR (1.2V/1.35V/1.8V), and dedicated rails for VDDCORE, VDDIO, and VDDFUSE - ensuring stable, efficient, and thermally optimized operation of ATSAMA5D26A-CUR in industrial applications.
ATSAMA5D26A-CUR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- 289-LFBGA
- Series:
- SAMA5D2
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A5
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 500MHz
- Co-Processors/DSP:
- Multimedia; NEON™ MPE
- RAM Controllers:
- LPDDR1, LPDDR2, LPDDR3, DDR2, DDR3, DDR3L, QSPI
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- Keyboard, LCD, Touchscreen
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 + HSIC
- Voltage - I/O:
- 3.3V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ, Boot Security, Cryptography, RTIC, Secure Fusebox, Secure JTAG, Secure Memory, Secure RTC
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 289-LFBGA (14x14)
- Additional Interfaces:
- I2C, SMC, SPI, UART, USART, QSPI
ATSAMA5D26A-CUR FAQ
1.How can I place an order for ATSAMA5D26A-CUR through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMA5D26A-CUR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMA5D26A-CUR reliable?
The price and inventory of ATSAMA5D26A-CUR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMA5D26A-CUR is usually 5 days.
3.What payment methods are accepted for ATSAMA5D26A-CUR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMA5D26A-CUR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMA5D26A-CUR?
ATSAMA5D26A-CUR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMA5D26A-CUR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMA5D26A-CUR?
For technical support, including ATSAMA5D26A-CUR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMA5D26A-CUR requirements.
6.How does Aetrix verify that ATSAMA5D26A-CUR is sourced from the original manufacturer or authorized distributors?
All ATSAMA5D26A-CUR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMA5D26A-CUR meets industry standards.
7.What is the process for return or replacement of ATSAMA5D26A-CUR?
All ATSAMA5D26A-CUR units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMA5D26A-CUR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMA5D26A-CUR part is unused and in its original packaging.
Return procedure for ATSAMA5D26A-CUR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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