Microchip Technology ATSAMA5D26B-CU

Overview

ATSAMA5D26B-CU from Microchip Technology is an ultra-low-power Arm Cortex-A5-based microprocessor unit (MPU) operating at up to 500 MHz, integrating DDR3L/LPDDR2/LPDDR3 memory controller, 10/100 Ethernet MAC (GMAC), dual CAN-FD controllers, USB high-speed host/device ports, and hardware crypto accelerators (AES-256, SHA-256, TRNG). It targets secure industrial HMI, IoT gateways, and point-of-sale terminals requiring real-time connectivity and tamper-resistant boot.

For engineers reviewing the ATSAMA5D26B-CU datasheet, ATSAMA5D26B-CU pinout, ATSAMA5D26B-CU application, or ATSAMA5D26B-CU equivalent, this page delivers verified technical context, validated package mapping (289-ball LFBGA, 14×14 mm, 0.8 mm pitch), confirmed security features (TrustZone, on-the-fly AESB encryption), and precise peripheral configuration (2 CAN-FD, 12-channel 12-bit ADC, 8×8 PTC).

Technical Context

The ATSAMA5D26B-CU implements a dual-bank 64-bit Advanced Interrupt Controller (AIC/SAIC), supports IEEE 802.1AS timestamping and 802.1Qav traffic shaping in its GMAC, and integrates two MCAN controllers with SRAM-based mailboxes and time-triggered transmission-though non-ISO CAN FD frame format prevents ISO 16845-1 conformance. Its memory subsystem includes a 128-Kbyte configurable L2 cache, 128-Kbyte scrambled internal SRAM, and DDR controller supporting DLL-off operation for DDR3L/LPDDR2/LPDDR3.

Power management includes three software-selectable low-power modes: Idle (CPU halted, peripherals active), Ultra-Low-Power (ULP0/ULP1 with partial asynchronous wake-up), and Backup mode with RTC and DDR self-refresh. Wake-up sources include nine dedicated pins, UART RX, analog comparators, and tamper detection on up to eight PIOBU lines.

Key Specifications

Pinout & Package

ATSAMA5D26B-CU is housed in a 289-ball LFBGA package (14×14 mm², 0.8 mm pitch) with 128 I/Os, each supporting up to eight peripheral functions via programmable multiplexing. The package supports full DDR3L/LPDDR2/LPDDR3 interface (32-bit data bus, differential clock/strobe), dual CAN-FD (CANRX0/CANTX0, CANRX1/CANTX1), GMAC (GTX0–GTX3, GRX0–GRX3, GMDC/GMDIO), and dedicated tamper/wake-up pins (PIOBU0–PIOBU7).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar MPU applications.

Compared with ATSAMA5D26B-CU, ATSAMA5D27B-CU reduces package size and peripheral count but sacrifices one CAN-FD channel and touch capability, while ATSAMA5D28B-CU adds environmental sensing and die shielding at identical pinout-making it a drop-in upgrade for enhanced physical security validation.

Availability

ATSAMA5D26B-CU is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, and medical data loggers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for production programs.

Supply support for ATSAMA5D26B-CU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology is a global semiconductor company delivering microcontrollers, analog components, and Flash-IP solutions with emphasis on reliability, security, and low-power design for industrial and automotive markets.

The SAMA5D2 product line targets secure, ultra-low-power embedded applications requiring Arm Cortex-A performance, hardware-accelerated cryptography, and industrial-grade connectivity-designed specifically for POS, IoT edge, and HMI systems demanding TrustZone isolation and tamper resistance.

FAQ

What is the maximum supported DDR memory type and speed for ATSAMA5D26B-CU?

ATSAMA5D26B-CU supports DDR3L, LPDDR2, and LPDDR3 memory types with DLL-off operation, enabling stable interface speeds up to 533 MT/s. The 32-bit DDR controller accommodates up to 512 Mbytes across 8 banks and integrates on-the-fly AESB encryption for DDR data paths-verified in DS60001476H-page 1.

Does ATSAMA5D26B-CU support ISO 16845-1 compliant CAN FD conformance testing?

No, ATSAMA5D26B-CU implements MCAN with non-ISO CAN FD frame format and therefore does not pass the CAN FD Conformance Test per ISO 16845-1:2016. This limitation is explicitly documented in the datasheet warning on page 1, and applies to both CAN0 and CAN1 channels.

How many tamper detection pins are available on ATSAMA5D26B-CU, and what happens upon detection?

ATSAMA5D26B-CU provides eight dedicated tamper/wake-up pins (PIOBU0–PIOBU7). Upon static or dynamic tamper detection, 1 Kbyte of secure SRAM is preserved while 4 Kbytes are erased, RTC timestamps the event, and the fuse box may be programmed to disable JTAG access-details confirmed in DS60001476H-page 2 and Table 1-1.

What power management ICs does Microchip recommend for ATSAMA5D26B-CU?

Microchip recommends MCP16502AA and MCP16501A PMICs for ATSAMA5D26B-CU. Both provide pin-selectable VDDIODDR (1.35V for DDR3L), leakage-free backup mode support, and I²C-controlled rail sequencing. MCP16502AA offers four 1A DC-DCs and two LDOs in 5×5 mm; MCP16501A delivers three 1A DC-DCs and one LDO in 4×4 mm QFN24-per DS60001476H-page 12–14.

Is ATSAMA5D26B-CU qualified for extended industrial temperature operation?

Yes, ATSAMA5D26B-CU is qualified for extended industrial temperature range operation from -40°C to +105°C ambient, as stated in the introduction section of DS60001476H-page 1. This qualification covers all core functionality including DDR3L interface, dual CAN-FD, GMAC, and crypto accelerators under full thermal stress conditions.