Microchip Technology ATSAMA5D26B-CUR

Overview

ATSAMA5D26B-CUR from Microchip Technology is an ultra-low-power Arm Cortex-A5-based microprocessor unit (MPU) operating at up to 500 MHz, featuring dual CAN-FD controllers, 10/100 Ethernet MAC with IEEE 1588 PTP support, LCD TFT controller (1024×768), and hardware crypto accelerators (AES-256, SHA-256, TRNG). It integrates 128 KB L2 cache configurable as SRAM, 128 KB internal scrambled SRAM, and supports DDR3L/LPDDR3 memory for industrial HMI and secure IoT gateway applications.

For engineers reviewing the ATSAMA5D26B-CUR datasheet, ATSAMA5D26B-CUR pinout, ATSAMA5D26B-CUR application, or ATSAMA5D26B-CUR equivalent, this page delivers verified technical context, validated package mapping (289-ball LFBGA, 14×14 mm, 0.8 mm pitch), confirmed low-power modes (ULP0/ULP1/Backup), real-world security features (TrustZone, tamper detection, on-the-fly AES encryption), and precise peripheral allocation per SAMA5D26 variant.

Technical Context

The ATSAMA5D26B-CUR implements a dual-core-capable Armv7-A architecture with TrustZone security extension, NEON SIMD engine, and floating-point unit (FPU) for deterministic real-time processing. Its multilayer bus matrix supports concurrent high-bandwidth transfers across DDR, QSPI, NAND, and peripherals via two 16-channel XDMAC controllers.

It integrates dedicated security hardware including a 5 KB tamper-protected SRAM (1 KB nonerasable), 8 tamper pins (PIOBU0–7), Integrity Check Monitor (ICM) with SHA-256, and AESB bridge enabling on-the-fly decryption of DDR/QSPI content - all aligned with IEC 60730 Class B safety requirements and FIPS 140-2/140-3 cryptographic compliance.

Key Specifications

Pinout & Package

ATSAMA5D26B-CUR is housed in a 289-ball LFBGA package (14×14 mm², 0.8 mm pitch) with 128 general-purpose I/Os multiplexed across eight peripheral functions per pin. The package supports full DDR3L/LPDDR3 interface routing, dual CAN transceiver connections, and dedicated power domains for VDDCORE (1.05 V), VDDIODDR (1.35 V), and VDDIO (3.3 V).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar MPU applications.

Compared with ATSAMA5D27B-CUR, the ATSAMA5D26B-CUR provides dual CAN-FD and ISC for industrial networking and vision edge use cases; versus i.MX6ULL, it delivers certified hardware security primitives (TrustZone, tamper SRAM, ICM) essential for regulated medical and utility deployments.

Availability

ATSAMA5D26B-CUR is available at Aetrix Electronics and suitable for industrial HMI terminals, secure IoT gateways, medical point-of-care devices, and smart energy metering hubs requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for ATSAMA5D26B-CUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology is a leading provider of microcontrollers, analog components, and Flash-IP solutions, with deep expertise in embedded security and industrial-grade reliability.

The SAMA5D2 product line was designed specifically for secure, ultra-low-power Linux-capable applications in industrial automation, IoT edge nodes, and medical devices - emphasizing hardware-enforced trust, cryptographic acceleration, and extended temperature operation.

FAQ

What is the maximum operating frequency of the ATSAMA5D26B-CUR?

The ATSAMA5D26B-CUR operates at up to 500 MHz on its Arm Cortex-A5 core. This frequency is sustained under typical thermal conditions with appropriate power delivery and cooling. The device also includes a 128 KB L2 cache configurable as SRAM and supports DDR3L/LPDDR3 memory interfaces running at up to 533 MHz data rate. All timing specifications are validated per DS60001476H.

Does the ATSAMA5D26B-CUR support CAN FD, and what is its conformance status?

Yes, the ATSAMA5D26B-CUR integrates two MCAN-FD controllers supporting non-ISO CAN FD frame format. As explicitly stated in the official datasheet, MCAN does not pass the ISO 16845-1:2016 CAN FD Conformance Test. Engineers must implement protocol-level validation in software or use external ISO-compliant transceivers for full standard compliance.

What security features are implemented in hardware on the ATSAMA5D26B-CUR?

The ATSAMA5D26B-CUR includes TrustZone-enabled memory isolation, 5 KB tamper-protected SRAM (1 KB nonerasable), 8 dedicated tamper pins (PIOBU0–7), Integrity Check Monitor (ICM) with SHA-256, on-the-fly AES-256 encryption/decryption for DDR/QSPI, and a ROM-based secure bootloader. These features collectively meet FIPS 140-2 Level 2 and IEC 60730 Class B requirements.

Which package type is used for the ATSAMA5D26B-CUR?

The ATSAMA5D26B-CUR uses a 289-ball LFBGA package measuring 14×14 mm² with 0.8 mm ball pitch and 1.4 mm thickness. This package supports full DDR3L/LPDDR3 routing, dual CAN, and 10/100 Ethernet interfaces. Pin compatibility is confirmed per Table 1-1 and Figure 2-1 in DS60001476H.

What low-power modes are available on the ATSAMA5D26B-CUR?

The ATSAMA5D26B-CUR offers three software-selectable low-power modes: Idle (CPU stopped, peripherals active), Ultra-Low-Power (ULP0/ULP1 with clock gating and partial wake-up), and Backup (RTC + wake logic active, DDR in self-refresh). Wake-up sources include up to nine PIO pins, UART reception, and analog comparator events - all documented in Section 3.3 of DS60001476H.