Microchip Technology ATSAMA5D26C-CUR

Overview

ATSAMA5D26C-CUR from Microchip Technology is an ultra-low-power Arm Cortex-A5-based microprocessor unit (MPU) operating at up to 500 MHz, integrating a 128-Kbyte L2 cache, 12-channel 12-bit ADC with resistive touchscreen support, dual CAN-FD controllers, and 10/100 Ethernet MAC with IEEE 1588 PTP. It targets secure industrial HMI, IoT gateways, and point-of-sale terminals requiring DDR3L/LPDDR3 memory, TrustZone isolation, and hardware crypto acceleration.

For engineers reviewing the ATSAMA5D26C-CUR datasheet, ATSAMA5D26C-CUR pinout, ATSAMA5D26C-CUR application, or ATSAMA5D26C-CUR equivalent, this page delivers verified technical context, validated package mapping (289-ball LFBGA), confirmed security features (AES-256, SHA-512, TRNG), real-world low-power modes (ULP0/ULP1/Backup), and precise peripheral configuration for SAMA5D26-series silicon.

Technical Context

The ATSAMA5D26C-CUR implements Armv7-A architecture with TrustZone-enabled memory protection, NEON SIMD engine for multimedia acceleration, and floating-point unit (FPU) for high-precision computation. Its multilayer bus architecture supports concurrent data transfers via two 16-channel XDMAC controllers and dedicated peripheral DMAs.

It integrates dual MCAN controllers compliant with non-ISO CAN FD frame format (not ISO 16845-1:2016 conformant), a 24-bit RGB LCD controller supporting 1024×768 resolution, and an Image Sensor Controller (ISC) handling up to 5-Mpixel sensors with Raw Bayer/JPEG interfaces. Security is enforced through on-the-fly AESB encryption of DDR/QSPI memory, Integrity Check Monitor (ICM), and tamper detection across eight PIOBU pins.

Key Specifications

Pinout & Package

ATSAMA5D26C-CUR is housed in a 289-ball LFBGA package (14×14 mm², 0.8 mm pitch). Pin functions are defined per the official SAMA5D2 Series signal description list, with full I/O multiplexing support across PA–PD banks and dedicated peripheral signal routing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar MPU applications.

Compared with ATSAMA5D26C-CUR, ATSAMA5D27C-CUR reduces package size and peripheral count but sacrifices ISC and dual CAN-FD; i.MX6ULL offers higher CPU frequency but lacks hardware security engines, TrustZone, and industrial temperature qualification-making it unsuitable for certified secure deployments.

Availability

ATSAMA5D26C-CUR is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, and medical data loggers requiring stable component supply, long-term lifecycle support, and traceable sourcing from authorized channels.

Supply support for ATSAMA5D26C-CUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology is a global semiconductor company delivering microcontrollers, analog components, FPGAs, and security solutions with emphasis on reliability, longevity, and embedded systems integration.

The SAMA5D2 product line targets secure, ultra-low-power Linux-capable MPUs for industrial, IoT, and medical edge devices-designed with hardware-enforced security, flexible memory interfaces, and comprehensive peripheral sets for human-machine interaction and connectivity.

FAQ

What is the maximum operating frequency of the ATSAMA5D26C-CUR?

The ATSAMA5D26C-CUR operates at up to 500 MHz on its Arm Cortex-A5 core. This frequency is achievable under typical conditions with appropriate voltage scaling and thermal management. The device also includes a 128-Kbyte configurable L2 cache and 32-Kbyte L1 instruction/data caches to sustain high throughput at this clock rate. ATSAMA5D26C-CUR's performance is validated across the full industrial temperature range (−40°C to +105°C).

Does the ATSAMA5D26C-CUR support ISO 16845-1:2016 CAN FD conformance testing?

No, the ATSAMA5D26C-CUR implements MCAN controllers using the non-ISO CAN FD frame format and does not pass the CAN FD Conformance Test per ISO 16845-1:2016. It supports time- and event-triggered transmission with SRAM-based mailboxes, but users requiring strict ISO compliance must implement external transceivers or protocol validation layers. ATSAMA5D26C-CUR's CAN functionality is intended for deterministic industrial networks where frame format flexibility is prioritized over standardized test compliance.

Which memory types are supported by the ATSAMA5D26C-CUR DDR controller?

The ATSAMA5D26C-CUR DDR controller supports DDR2, DDR3, DDR3L, LPDDR1, LPDDR2, and LPDDR3 memory with up to 512 Mbytes capacity. It operates in 16-bit or 32-bit mode and includes "on-the-fly" AES encryption/decryption for DDR and QSPI memories. ATSAMA5D26C-CUR requires external memory configuration via the SDRAM controller registers and supports DLL-off operation for DDR3L and DDR2 variants.

How many tamper detection pins does the ATSAMA5D26C-CUR provide?

The ATSAMA5D26C-CUR provides eight dedicated tamper detection pins (PIOBU0–PIOBU7) for static or dynamic intrusion monitoring. These pins feed into the Security Module and can trigger immediate erasure of 1-Kbyte nonerasable and 4-Kbyte erasable scrambled SRAM upon tamper event detection. ATSAMA5D26C-CUR also supports environmental monitors (temperature/voltage/frequency) on select versions, though those require NDA-restricted documentation.

Is the ATSAMA5D26C-CUR qualified for extended industrial temperature operation?

Yes, the ATSAMA5D26C-CUR is qualified for extended industrial temperature operation from −40°C to +105°C ambient. This rating applies to the full feature set-including DDR3L/LPDDR3 memory interface, dual CAN-FD, 10/100 EMAC, and hardware crypto accelerators-as verified in Microchip's official characterization reports. ATSAMA5D26C-CUR's thermal design supports sustained 500 MHz operation within this range when paired with recommended PMICs like MCP16502AA.