Microchip Technology ATSAMA5D27A-CU

Overview

ATSAMA5D27A-CU from Microchip Technology is an ultra-low-power Arm Cortex-A5-based microprocessor unit (MPU) operating at up to 500 MHz, integrating a 128-Kbyte configurable L2 cache, 12-channel 12-bit ADC with resistive touchscreen support, dual CAN-FD controllers, and 10/100 Ethernet MAC with IEEE 802.1AS timestamping. It targets secure industrial HMI, IoT gateways, and point-of-sale terminals requiring cryptographic acceleration and TrustZone-secured boot.

For engineers reviewing the ATSAMA5D27A-CU datasheet, ATSAMA5D27A-CU pinout, ATSAMA5D27A-CU application, or ATSAMA5D27A-CU equivalent, this page delivers verified technical context, validated package mapping (289-ball LFBGA), confirmed security features (AES-256, SHA-512, TRNG), low-power modes (ULP0/ULP1/Backup), and real-world peripheral integration including LCDC, ISC, and dual QSPI interfaces.

Technical Context

The ATSAMA5D27A-CU implements an Armv7-A architecture Cortex-A5 core with NEON SIMD engine and floating-point unit, paired with a multilayer bus matrix supporting concurrent DDR3L/LPDDR3 access and on-the-fly AES encryption/decryption for DDR and QSPI memories. Its memory subsystem includes 32-Kbyte L1 instruction and data caches, 128-Kbyte L2 cache configurable as SRAM, and 128-Kbyte scrambled internal SRAM.

Security is enforced via Arm TrustZone, hardware-accelerated crypto engines (AES-256, SHA-512, TDES, TRNG), Integrity Check Monitor (ICM), tamper detection across eight PIOBU pins, and secure bootloader in 64-Kbyte scrambled ROM. Peripheral control uses a hierarchical interrupt system with 64-bit AIC and SAIC, plus an Event System enabling autonomous peripheral interaction without CPU intervention.

Key Specifications

Pinout & Package

ATSAMA5D27A-CU is housed in a 289-ball LFBGA package (14×14 mm², 0.8 mm pitch). Pin functions are defined per the official SAMA5D2 Series signal description list, with dedicated banks for DDR, QSPI, SDMMC, FLEXCOM, CAN, USB, GMAC, and security-critical signals (PIOBU0–7, SHDN, NRST).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar MPU applications.

Compared with ATSAMA5D27A-CU, ATSAMA5D26A-CU lacks AESB and tamper detection but reduces footprint; ATSAMA5D28A-CU adds environmental sensors and die shield for certified safety applications, increasing thermal and layout complexity.

Availability

ATSAMA5D27A-CU is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, and point-of-sale terminals requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for production programs.

Supply support for ATSAMA5D27A-CU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology is a global semiconductor company delivering microcontrollers, analog, FPGA, and security solutions with emphasis on reliability, longevity, and embedded systems integration.

The SAMA5D2 product line was designed for secure, ultra-low-power Linux-capable MPUs targeting industrial automation, IoT edge nodes, and human-machine interfaces where cryptographic acceleration, TrustZone isolation, and extended temperature operation are critical.

FAQ

What is the maximum DDR memory configuration supported by ATSAMA5D27A-CU?

ATSAMA5D27A-CU supports up to 512 Mbytes of DDR3L or LPDDR3 memory via its 32-bit DDR controller. The interface operates with DLL-off timing and includes hardware-based ECC support, on-the-fly AES encryption/decryption (AESB), and calibration logic for DDR/LPDDR signal integrity. This enables robust, secure memory access for Linux workloads without software-level crypto overhead.

Does ATSAMA5D27A-CU support CAN FD, and what are its limitations?

ATSAMA5D27A-CU integrates two MCAN controllers supporting CAN FD frame formats, but they implement the non-ISO CAN FD specification and do not pass the ISO 16845-1:2016 conformance test. These controllers provide SRAM-based mailboxes, time-triggered transmission, and event-triggered transmission-ideal for deterministic industrial networks-but require protocol stack validation against non-ISO FD implementations.

How does ATSAMA5D27A-CU achieve secure boot and runtime integrity verification?

ATSAMA5D27A-CU executes secure boot from 64-Kbyte scrambled ROM containing a verified bootloader, with fuse-controlled JTAG disable and BMS key storage. Runtime integrity is enforced by the Integrity Check Monitor (ICM), which performs SHA256 hashing of external and internal memory regions-including QSPI and DDR-and triggers tamper response if hash mismatches occur, ensuring only authenticated code executes.

What low-power modes are available on ATSAMA5D27A-CU, and how do they differ?

ATSAMA5D27A-CU offers three software-selectable low-power modes: Idle (CPU halted, peripherals active), Ultra-Low-Power (ULP0/ULP1 with clocks scaled or stopped, partial asynchronous wake-up), and Backup (RTC + wake logic active, DDR in self-refresh). ULP1 stops all clocks except RTC and supports wake-up from nine pins, UART, or analog comparators-enabling sub-100 µA standby current with full state retention in 5-Kbyte SRAM.

Which power management ICs are officially recommended for ATSAMA5D27A-CU?

Microchip recommends MCP16502AA and MCP16501A PMICs for ATSAMA5D27A-CU. MCP16502AA provides four 1A DC-DC buck regulators and two 0.3A LDOs with I²C interface, supporting DDR3L (1.35V) and core rails (1.25V/3.3V). MCP16501A offers a space-optimized 4-channel solution in 4×4 mm QFN24, with pin-selectable VDDIODDR voltage and leakage-free backup mode operation.