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Microchip Technology ATSAMA5D27B-CNR
- Part No.:
- ATSAMA5D27B-CNR
- Manufacturer:
- Microchip Technology
- Category:
- Microprocessors
- Package:
- 289-LFBGA
- Datasheet:
-
ATSAMA5D27B-CNR.pdf
- Description:
- IC MPU SAMA5D2 500MHZ 289LFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:1,703
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Product details
Overview
ATSAMA5D27B-CNR from Microchip Technology is an ultra-low-power Arm® Cortex®-A5-based microprocessor unit (MPU) operating at up to 500 MHz, integrating a 10/100 Ethernet MAC, dual CAN-FD controllers, USB high-speed host/device ports, LCD TFT controller, and hardware crypto accelerators (AES-256, SHA-256, TRNG). It supports DDR2/DDR3L/LPDDR2/LPDDR3 memory and targets secure industrial HMI, IoT gateways, and point-of-sale terminals.
For engineers reviewing the ATSAMA5D27B-CNR datasheet, ATSAMA5D27B-CNR pinout, ATSAMA5D27B-CNR application, or ATSAMA5D27B-CNR equivalent, this page delivers verified technical context, validated package mapping (289-ball LFBGA), confirmed security features (Arm TrustZone®, tamper detection, on-the-fly AES DDR encryption), and real-world low-power mode behavior (ULP0/ULP1/Backup with DDR self-refresh).
Technical Context
The ATSAMA5D27B-CNR implements a full Armv7-A architecture with MMU, NEON SIMD engine, and FPU for Linux-capable embedded computing. It integrates dual MCAN controllers supporting non-ISO CAN FD frame format with SRAM-based mailboxes and time-triggered transmission - distinct from ISO 16845-1-compliant CAN FD.
Its memory subsystem includes a high-bandwidth 32-bit DDR controller (up to 512 MB), dual QSPI interfaces, SDMMC0/SDMMC1 hosts (eMMC 4.51/4.41), and 128 KB configurable L2 cache usable as internal SRAM. Security is enforced via Arm TrustZone®, 5 KB scrambled secure SRAM (1 KB nonerasable on tamper), and Integrity Check Monitor (ICM) with SHA256.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-A5 @ up to 500 MHz with NEON, FPU, and TrustZone support for secure OS partitioning |
| Memory Interface | 32-bit DDR2/DDR3L/LPDDR2/LPDDR3 controller supporting up to 512 MB with on-the-fly AES encryption/decryption path |
| Security Features | Hardware AES-256/SHA-256/TRNG, 5 KB tamper-responsive scrambled SRAM, 8 tamper pins, ICM-based memory integrity verification |
| Connectivity | Dual MCAN (non-ISO CAN FD), 10/100 EMAC with IEEE 802.1AS/1588 PTP, USB UDPHS + UHPHS (or dual UHPHS), HSIC interface |
| User Interface | 24-bit RGB LCD TFT controller (1024×768), ITU-R BT.601/656/1120 ISC supporting 5 MPixel sensors, 8×8 capacitive PTC |
| Low-Power Modes | Three software-selectable modes: Idle (CPU stopped), ULP0/ULP1 (asynchronous wake-up from 9 pins/UART/analog compare), Backup with DDR self-refresh |
| Package | 289-ball LFBGA, 14×14 mm², 0.8 mm pitch, 1.4 mm thickness - matches SAMA5D27 configuration in DS60001476H |
Pinout & Package
ATSAMA5D27B-CNR is housed in a 289-ball LFBGA package (14×14 mm², 0.8 mm pitch), compatible with the SAMA5D27 variant per Table 1-1 and Figure 2-1 of DS60001476H. Pin functions align with the full SAMA5D2 series signal set including PA–PD I/O banks, DDR_D[31:0], GMAC, CANRX/CANTX, SDMMCx_DAT[7:0], QSPIx_IO[0..3], and dedicated tamper/wake-up pins PIOBU0–PIOBU7.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PA0–PA31, PB0–PB31, PC0–PC31, PD0–PD31 | Programmable I/O bank | 128 total GPIOs with up to 8 peripheral functions per pin; supports synchronous 32-bit output writes and resistive touchscreen ADC inputs AD0–AD11 |
| DDR_D[31:0], DDR_A[13:0], DDR_BA[2:0], DDR_CK/DDR_CLKN | DDR memory bus interface | 32-bit data, 14-bit address, 3-bit bank select, differential clock - enables direct connection to DDR3L/LPDDR3 SDRAM without external logic |
| CANRX0/CANTX0, CANRX1/CANTX1 | MCAN controller physical interface | Dual independent CAN-FD transceiver interfaces compliant with non-ISO frame format; require external CAN transceivers (e.g., ATA6560) |
| GTX0–GTX3, GRX0–GRX3, GMDC/GMDIO | 10/100 Ethernet PHY interface | RMII/MII-compatible parallel interface; supports IEEE 802.1AS timestamping and 1588 PTP hardware assist for deterministic networking |
| SDMMC0_DAT[7:0], SDMMC0_CMD, SDMMC0_CK | e.MMC/SD 3.0 host interface | 8-bit eMMC 4.51 interface with 1.8V signaling support; enables boot-from-eMMC and high-throughput storage |
| QSPI0_IO[0..3], QSPI1_IO[0..3] | Quad SPI flash interface | Dual independent QSPI controllers supporting XIP (execute-in-place) and on-the-fly decryption of encrypted firmware images |
Key Features
| Feature | Design Value |
|---|---|
| Arm TrustZone-enabled secure world isolation | Hardware-enforced separation between secure/non-secure code execution and memory access - foundational for secure bootloader and trusted applications |
| On-the-fly AESB encryption/decryption engine | Real-time decryption of code/data stored in DDR or QSPI memory without CPU overhead - enables secure firmware updates and IP protection |
| Dual MCAN controllers with SRAM mailboxes | Independent CAN FD message buffers with time-triggered transmission scheduling - eliminates host CPU polling for deterministic automotive/IoT messaging |
| 12-channel 12-bit ADC with resistive touchscreen support | Integrated touch digitizer with 5-wire resistive overlay capability - reduces BOM by eliminating external touch controller IC |
| Event System for peripheral-to-peripheral communication | Hardware event routing between peripherals (e.g., timer → PWM → ADC trigger) without CPU intervention - lowers power and latency in sensor/control loops |
| Extended Backup mode with DDR self-refresh | Retains full DDR contents while CPU and most clocks are halted - enables sub-10 µA sleep current with instant resume from external events |
Applications
| Industrial HMI Terminal | Secure IoT Gateway |
|---|---|
Use Scenario: Factory-floor human-machine interface with local display, touch input, and fieldbus connectivity. IC Role / Device Role / Timing Role: Main application processor running Linux with Qt-based GUI, managing LCD TFT, PTC, dual CAN, and EMAC for PLC integration. Use Value: Integrated 24-bit RGB LCD controller and 8×8 PTC eliminate external display/touch ICs; dual CAN-FD enables direct connection to industrial motion controllers. |
Use Scenario: Edge gateway aggregating sensor data from Modbus/CAN networks and forwarding to cloud via TLS-secured Ethernet/Wi-Fi. IC Role / Device Role / Timing Role: Secure application host executing authenticated firmware, performing AES-256 encryption of sensor payloads before transmission. Use Value: Hardware TRNG and SHA-256 accelerate TLS handshake; ICM validates boot image integrity to prevent unauthorized firmware execution. |
| Point-of-Sale (POS) Terminal | Medical Data Logger |
Use Scenario: PCI-compliant payment terminal with magnetic stripe, EMV chip, and contactless reader interfaces. IC Role / Device Role / Timing Role: Root-of-trust MPU enforcing secure boot, managing encrypted eMMC storage for transaction logs, and isolating payment apps via TrustZone. Use Value: 5 KB tamper-responsive SRAM stores cryptographic keys erased on physical intrusion; AESB encrypts cardholder data in DDR before logging. |
Use Scenario: Battery-powered patient monitor recording ECG, temperature, and SpO₂ with long-term data retention. IC Role / Device Role / Timing Role: Ultra-low-power controller using Backup mode with DDR self-refresh to retain waveform buffers during sleep, waking only for ADC sampling. Use Value: ULP1 mode achieves sub-10 µA quiescent current; integrated 12-bit ADC with resistive touchscreen supports dual-use UI/data acquisition on same PCB area. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMA5D26B-CNR | 196-ball TFBGA, 105 GPIOs, single CAN, no ISC, no PTC, 128 KB L2 cache only (no SRAM config) | Lacks camera interface and capacitive touch - suitable for headless gateways or simple HMI without imaging/touch | Select when footprint, cost, or peripheral count must be reduced; verify DDR interface compatibility (16-bit vs. 32-bit) |
| i.MX6ULL | Arm Cortex-A7 @ 900 MHz, single ENET, no CAN-FD, no hardware crypto acceleration (SW-only AES/SHA), 14x14 mm 289-BGA but different pinout | Higher CPU clock but no TrustZone-enforced secure world; requires external crypto co-processor for TLS offload | Choose for Linux performance-critical apps without strict security or CAN-FD requirements; expect layout redesign due to incompatible pin mapping |
Compared with ATSAMA5D26B-CNR, the ATSAMA5D27B-CNR adds dual CAN-FD, ISC, and PTC for richer connectivity and UI - while i.MX6ULL trades hardware security and deterministic peripherals for raw CPU throughput, demanding external components to match ATSAMA5D27B-CNR's integrated capabilities.
Availability
ATSAMA5D27B-CNR is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, and medical data loggers requiring stable component supply, long lifecycle assurance, and qualified extended temperature operation (-40°C to +105°C).
Supply support for ATSAMA5D27B-CNR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog, FPGA, and security solutions, with strong focus on industrial, automotive, and IoT markets.
The SAMA5D2 product line delivers ultra-low-power, Linux-capable MPUs with hardware-enforced security and rich peripheral integration - designed specifically for secure edge devices where trust, longevity, and deterministic I/O matter.
FAQ
What is the maximum DDR memory capacity supported by the ATSAMA5D27B-CNR?
The ATSAMA5D27B-CNR supports up to 512 Mbytes of DDR2/DDR3L/LPDDR2/LPDDR3 memory via its high-bandwidth 32-bit DDR controller. This capacity is achievable with 8-bank configurations and DLL-off operation as specified in DS60001476H, enabling robust application workloads in industrial and gateway use cases where ATSAMA5D27B-CNR serves as the primary compute engine.
Does the ATSAMA5D27B-CNR support ISO 16845-1-compliant CAN FD?
No, the ATSAMA5D27B-CNR implements MCAN controllers using the non-ISO CAN FD frame format and does not pass the ISO 16845-1:2016 conformance test. Its dual MCAN modules support SRAM-based mailboxes and time-triggered transmission but require external ISO-compliant transceivers and software adaptation for interoperability with standard CAN FD networks - a key distinction documented in the SAMA5D2 Series datasheet for ATSAMA5D27B-CNR.
How does the ATSAMA5D27B-CNR achieve secure boot?
The ATSAMA5D27B-CNR enables secure boot through a combination of hardware features: a 64-Kbyte scrambled and maskable ROM embedding the secure bootloader, 5 KB of tamper-responsive scrambled SRAM to store keys, and Integrity Check Monitor (ICM) with SHA256 to verify boot image authenticity. These elements - all confirmed for ATSAMA5D27B-CNR in DS60001476H - form a root-of-trust chain that prevents unauthorized firmware execution.
What power management ICs are recommended for the ATSAMA5D27B-CNR?
Microchip recommends the MCP16502AA and MCP16501A PMICs for ATSAMA5D27B-CNR. Both provide pin-selectable VDDIODDR (1.2V/1.35V/1.8V) to match DDR3L/LPDDR3 memory, leakage-free backup mode support, and I²C-controlled rail sequencing. The MCP16502AA adds a fourth buck regulator and dual LDOs, while MCP16501A offers a compact 4×4 mm QFN24 footprint - both validated in application schematics for ATSAMA5D27B-CNR systems.
Can the ATSAMA5D27B-CNR operate in extended temperature range?
Yes, the ATSAMA5D27B-CNR is qualified for extended industrial temperature operation from -40°C to +105°C ambient, as explicitly stated in the SAMA5D2 Series introduction and confirmed across all SAMA5D27 variants in DS60001476H. This rating applies to the full 289-ball LFBGA package and supports deployment in harsh environments such as factory automation, outdoor gateways, and transportation systems where ATSAMA5D27B-CNR serves as the central processing unit.
ATSAMA5D27B-CNR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- 289-LFBGA
- Series:
- SAMA5D2
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Core Processor:
- ARM® Cortex®-A5
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 500MHz
- Co-Processors/DSP:
- Multimedia; NEON™ MPE
- RAM Controllers:
- LPDDR1, LPDDR2, LPDDR3, DDR2, DDR3, DDR3L, QSPI
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- Keyboard, LCD, Touchscreen
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 + HSIC
- Voltage - I/O:
- 3.3V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ, Boot Security, Cryptography, RTIC, Secure Fusebox, Secure JTAG, Secure Memory, Secure RTC
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 289-LFBGA (14x14)
- Additional Interfaces:
- I2C, SMC, SPI, UART, USART, QSPI
ATSAMA5D27B-CNR FAQ
1.How can I place an order for ATSAMA5D27B-CNR through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMA5D27B-CNR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMA5D27B-CNR reliable?
The price and inventory of ATSAMA5D27B-CNR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMA5D27B-CNR is usually 5 days.
3.What payment methods are accepted for ATSAMA5D27B-CNR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMA5D27B-CNR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMA5D27B-CNR?
ATSAMA5D27B-CNR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMA5D27B-CNR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMA5D27B-CNR?
For technical support, including ATSAMA5D27B-CNR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMA5D27B-CNR requirements.
6.How does Aetrix verify that ATSAMA5D27B-CNR is sourced from the original manufacturer or authorized distributors?
All ATSAMA5D27B-CNR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMA5D27B-CNR meets industry standards.
7.What is the process for return or replacement of ATSAMA5D27B-CNR?
All ATSAMA5D27B-CNR units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMA5D27B-CNR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMA5D27B-CNR part is unused and in its original packaging.
Return procedure for ATSAMA5D27B-CNR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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