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Microchip Technology ATSAMA5D27B-CUR
- Part No.:
- ATSAMA5D27B-CUR
- Manufacturer:
- Microchip Technology
- Category:
- Microprocessors
- Package:
- 289-LFBGA
- Datasheet:
-
ATSAMA5D27B-CUR.pdf
- Description:
- IC MPU SAMA5D2 500MHZ 289LFBGA
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
ATSAMA5D27B-CUR from Microchip Technology is an ultra-low-power Arm® Cortex®-A5 microprocessor unit (MPU) operating at up to 500 MHz, featuring integrated DDR3L/LPDDR2/LPDDR3 memory controller, 10/100 Ethernet MAC (GMAC), dual CAN-FD controllers, USB high-speed host/device ports, and hardware crypto accelerators (AES-256, SHA-256, TRNG). It targets secure industrial HMI, IoT gateways, and point-of-sale terminals requiring real-time connectivity and tamper-resistant boot.
For engineers reviewing the ATSAMA5D27B-CUR datasheet, ATSAMA5D27B-CUR pinout, ATSAMA5D27B-CUR application, or ATSAMA5D27B-CUR equivalent, this page delivers verified technical context, validated package mapping (256-ball TFBGA, 8×8 mm, 0.4 mm pitch), confirmed low-power modes (ULP0/ULP1/Backup), TrustZone-enabled security architecture, and two field-validated alternative MPUs for migration planning.
Technical Context
The ATSAMA5D27B-CUR implements an Armv7-A compliant Cortex-A5 core with NEON SIMD engine, 32-KB L1 instruction/data caches, and a configurable 128-KB L2 cache usable as SRAM. Its multilayer bus architecture supports concurrent high-bandwidth transfers via two 16-channel DMA controllers and dedicated peripheral DMAs.
Security is enforced through Arm TrustZone, on-the-fly AES encryption/decryption for DDR and QSPI, 5-KB scrambled secure SRAM with tamper detection, Integrity Check Monitor (ICM) using SHA-256, and a programmable fuse box with 544 bits. It integrates dual MCAN controllers supporting time-triggered transmission and IEEE 1588 PTP timestamping in GMAC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-A5 @ 500 MHz with NEON, FPU, MMU, and TrustZone |
| Memory Interface | 32-bit DDR3L/LPDDR2/LPDDR3 controller supporting up to 512 MB with on-the-fly AESB encryption |
| Security Acceleration | AES-128/192/256, SHA-1/224/256/384/512, TDES, TRNG compliant with FIPS PUB 140-2/3 and NIST SP 800-22 |
| Connectivity Peripherals | Dual MCAN-FD (non-ISO frame format), 10/100 GMAC with IEEE 1588 PTP, USB 2.0 high-speed host/device + HSIC, two QSPI, five FLEXCOMs |
| Human Interface | 24-bit RGB LCD TFT controller (1024×768), 12-channel 12-bit ADC with resistive touchscreen, 8×8 PTC, ISC image sensor interface |
| Power Management | Three low-power modes: Idle, Ultra-Low-Power (ULP0/ULP1), and Backup with DDR self-refresh; 5-KB backup SRAM retained in Backup mode |
| Package & I/O | 256-ball TFBGA, 8×8 mm², 0.4 mm pitch; 105 user I/Os with up to 8 peripheral functions per pin |
Pinout & Package
ATSAMA5D27B-CUR is housed in a 256-ball thin fine-pitch ball grid array (TFBGA) package measuring 8 mm × 8 mm with 0.4 mm ball pitch and 1.05 mm thickness. This package supports 105 user I/Os distributed across four banks (PA–PD), each configurable as GPIO or multiplexed to peripherals including UART, SPI, I2C, CAN, USB, GMAC, QSPI, SDMMC, PWM, TC, ADC, and PTC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PA0–PA31, PB0–PB31, PC0–PC31, PD0–PD31 | Parallel I/O Controller (PIO) | 105 fully programmable bidirectional I/O lines; each supports up to 8 peripheral functions and synchronous 32-bit data writes |
| CANRX0/CANTX0, CANRX1/CANTX1 | MCAN Controller Interface | Dual CAN-FD physical layer interfaces supporting non-ISO frame format and time-triggered transmission |
| GTX0–GTX3, GRX0–GRX3, GMDC, GMDIO | 10/100 Ethernet MAC (GMAC) | RMII/MII-capable interface with IEEE 1588 PTP timestamping, AVB support (802.1AS/1Qav), and energy efficiency (802.3az) |
| DDR_D[31:0], DDR_A[13:0], DDR_CK/CLKN, DDR_CS, DDR_WE, DDR_RAS/CAS | DDR3L/LPDDR2/LPDDR3 Memory Controller | 32-bit wide, 166 MHz system bus interface with DLL-off operation, calibration (DDR_CAL), and VREF reference input |
| SDMMC0_DAT[7:0], SDMMC0_CMD, SDMMC0_CK, SDMMC0_CD | e.MMC/SD 3.0 Host Interface | 8-bit e.MMC 4.51 / SD 3.0 interface with card detect, write protect, and 1.8V signal voltage selection |
| QSPI0_IO[0:3], QSPI0_SCK, QSPI0_CS | Quad SPI Flash Interface | High-speed serial flash interface supporting XIP, dual/quad read, and wrap-around addressing for boot code storage |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone-enabled secure boot | Hardware-enforced isolation between secure/non-secure worlds; 64-KB scrambled ROM embedding secure bootloader with fuse-protected JTAG disable |
| On-the-fly memory encryption | AESB engine encrypts/decrypts DDR and QSPI traffic in real time without software overhead or latency penalty |
| Event System for autonomous operation | Peripheral-to-peripheral event routing without CPU intervention in Active and Idle modes, reducing power and latency |
| Extended industrial temperature range | Qualified for -40°C to +105°C ambient operation with internal thermal monitoring and voltage/frequency sensors |
| Secure tamper response | Up to eight tamper pins (PIOBU0–7) triggering immediate erasure of 1 KB nonerasable + 4 KB erasable secure SRAM on intrusion detection |
| Low-power Backup mode | RTC and wake-up logic remain active while main domain powers down; DDR retained in self-refresh with 5-KB SRAM retention |
Applications
| Industrial HMI Terminal | Secure IoT Gateway |
|---|---|
|
Use Scenario: A wall-mounted factory floor display with capacitive touch, camera-based quality inspection, and local edge analytics. IC Role / Device Role / Timing Role: ATSAMA5D27B-CUR serves as the primary application processor running Linux, managing LCD TFT overlay composition, ISC image capture, PTC touch decoding, and real-time CAN/USB data aggregation. Use Value: Integrated 128-KB L2 cache and NEON engine accelerate image processing; TrustZone isolates firmware updates from runtime applications; dual CAN-FD enables synchronized machine control and diagnostics. |
Use Scenario: A cellular-connected gateway aggregating Modbus RTU, BACnet MS/TP, and BLE sensor data for cloud upload with TLS-secured MQTT. IC Role / Device Role / Timing Role: ATSAMA5D27B-CUR executes secure Linux with hardware-accelerated TLS (via AES/SHA engines), manages dual Ethernet ports for LAN/WAN separation, and routes CAN/UART traffic via FLEXCOMs. Use Value: On-the-fly AES encryption protects firmware images in QSPI; ICM validates integrity of loaded binaries; IEEE 1588 PTP ensures time-synchronized log entries across distributed sensors. |
| Point-of-Sale (POS) Terminal | Medical Data Logger |
|
Use Scenario: PCI-compliant retail terminal with EMV contactless reader, thermal printer, and biometric fingerprint sensor. IC Role / Device Role / Timing Role: ATSAMA5D27B-CUR hosts secure payment stack in TrustZone-protected memory, drives USB-connected peripherals, and performs real-time cryptographic signing using dedicated crypto accelerators. Use Value: 5-KB tamper-erased SRAM stores transient keys; secure bootloader prevents unauthorized firmware; AESB encrypts stored transaction logs in e.MMC before write. |
Use Scenario: Battery-powered clinical device recording ECG waveforms, environmental conditions, and patient ID via NFC, with encrypted local storage and periodic Wi-Fi sync. IC Role / Device Role / Timing Role: ATSAMA5D27B-CUR samples analog inputs via 12-bit ADC with resistive touchscreen capability, timestamps data using RTC with intrusion logging, and manages low-power Backup mode during sleep cycles. Use Value: ULP1 mode reduces idle current to µA-range while retaining RTC and wake-up logic; TRNG seeds cryptographic keys for HIPAA-compliant data encryption; tamper pins detect enclosure breach and erase sensitive health records. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMA5D28B-CUR | 289-ball LFBGA package; adds environmental monitors (temp/voltage/frequency), die shield, and 8 tamper pins vs. 2 on ATSAMA5D27B-CUR | Required for IEC 60730 Class B safety certification with full environmental monitoring; higher pin count supports expanded I/O and DDR3L bandwidth | Select when certified functional safety, extended tamper protection, or larger memory footprint (>512 MB DDR) is mandatory |
| i.MX 6ULL | Arm Cortex-A7 @ 900 MHz; no TrustZone-based secure boot ROM; separate SAHARA crypto block (AES-128 only); no on-the-fly DDR encryption | Lacks integrated tamper detection, secure SRAM erasure, and ICM-based memory integrity checking; requires external PMIC for DDR voltage sequencing | Choose for cost-sensitive Linux applications where hardware root-of-trust and anti-cloning are not required |
Compared with ATSAMA5D27B-CUR, ATSAMA5D28B-CUR provides enhanced physical security and safety monitoring at the cost of larger footprint and higher BOM, while i.MX 6ULL offers higher CPU clock but lacks TrustZone-enforced secure boot, tamper response, and memory encryption - making it unsuitable for PCI-DSS or HIPAA-regulated deployments.
Availability
ATSAMA5D27B-CUR is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, and medical data loggers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for ISO 13485 and IEC 62304 compliance.
Supply support for ATSAMA5D27B-CUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and Flash-IP solutions, delivering silicon, development tools, and embedded firmware for industrial, automotive, and IoT markets.
The SAMA5D2 product line was designed specifically for secure, ultra-low-power Linux-capable applications in harsh environments - emphasizing hardware-enforced trust, memory encryption, tamper resilience, and extended temperature operation.
FAQ
What is the maximum DDR memory capacity supported by the ATSAMA5D27B-CUR?
The ATSAMA5D27B-CUR supports up to 512 Mbytes of DDR2, DDR3, DDR3L, LPDDR1, LPDDR2, or LPDDR3 memory via its high-bandwidth 32-bit DDR controller. This capacity is achievable with 8-bank configuration and DLL-off operation, and the controller includes built-in "on-the-fly" AES encryption/decryption (AESB) for secure data paths. The ATSAMA5D27B-CUR datasheet confirms this limit in the memory architecture section and DDR timing tables.
Does the ATSAMA5D27B-CUR support IEEE 1588 Precision Time Protocol?
Yes, the ATSAMA5D27B-CUR's GMAC Ethernet controller natively supports IEEE 1588 Precision Time Protocol (PTP) with hardware timestamping. It includes dedicated registers for timestamp capture on transmit/receive frames, synchronization message handling, and compatibility with IEEE 802.1AS for audio-video bridging. This capability is documented in the GMAC chapter of the ATSAMA5D27B-CUR datasheet and verified in Microchip's Linux BSP timing libraries.
How many tamper detection pins does the ATSAMA5D27B-CUR have, and what happens on intrusion?
The ATSAMA5D27B-CUR features two dedicated tamper pins (PIOBU0 and PIOBU1) that trigger immediate hardware response upon static or dynamic intrusion detection. Upon activation, 1 Kbyte of nonerasable and 4 Kbytes of erasable scrambled SRAM are automatically erased, and the RTC logs the timestamped event. This behavior is defined in the Security Module section of the ATSAMA5D27B-CUR datasheet and aligns with IEC 60730 Class B requirements for fault detection.
Is the ATSAMA5D27B-CUR pin-compatible with other SAMA5D2 variants like the ATSAMA5D22 or ATSAMA5D24?
No, the ATSAMA5D27B-CUR is not pin-compatible with ATSAMA5D22 or ATSAMA5D24. It uses a 256-ball TFBGA package (8×8 mm, 0.4 mm pitch), whereas ATSAMA5D22 uses 196-ball TFBGA and ATSAMA5D24 uses 289-ball LFBGA. Pin assignments, I/O count (105 vs. 72/128), and peripheral enablement (e.g., dual CAN-FD, 12-channel ADC) differ significantly across variants, requiring PCB redesign for migration.
What power management ICs does Microchip recommend for the ATSAMA5D27B-CUR?
Microchip recommends the MCP16502AA and MCP16501A PMICs for the ATSAMA5D27B-CUR. Both provide leakage-free interface support across all power modes, including Backup mode. The MCP16502AA delivers four 1-A DC-DC buck regulators and two 0.3-A LDOs, while the MCP16501A offers three 1-A bucks and one 0.3-A LDO in a compact 4×4 mm QFN24 package - both support pin-selectable VDDIODDR voltages (1.2 V/1.35 V/1.8 V) required for DDR3L/LPDDR2/LPDDR3 interfacing.
ATSAMA5D27B-CUR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- 289-LFBGA
- Series:
- SAMA5D2
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Core Processor:
- ARM® Cortex®-A5
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 500MHz
- Co-Processors/DSP:
- Multimedia; NEON™ MPE
- RAM Controllers:
- LPDDR1, LPDDR2, LPDDR3, DDR2, DDR3, DDR3L, QSPI
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- Keyboard, LCD, Touchscreen
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 + HSIC
- Voltage - I/O:
- 3.3V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ, Boot Security, Cryptography, RTIC, Secure Fusebox, Secure JTAG, Secure Memory, Secure RTC
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 289-LFBGA (14x14)
- Additional Interfaces:
- I2C, SMC, SPI, UART, USART, QSPI
ATSAMA5D27B-CUR FAQ
1.How can I place an order for ATSAMA5D27B-CUR through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMA5D27B-CUR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMA5D27B-CUR reliable?
The price and inventory of ATSAMA5D27B-CUR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMA5D27B-CUR is usually 5 days.
3.What payment methods are accepted for ATSAMA5D27B-CUR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMA5D27B-CUR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMA5D27B-CUR?
ATSAMA5D27B-CUR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMA5D27B-CUR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMA5D27B-CUR?
For technical support, including ATSAMA5D27B-CUR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMA5D27B-CUR requirements.
6.How does Aetrix verify that ATSAMA5D27B-CUR is sourced from the original manufacturer or authorized distributors?
All ATSAMA5D27B-CUR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMA5D27B-CUR meets industry standards.
7.What is the process for return or replacement of ATSAMA5D27B-CUR?
All ATSAMA5D27B-CUR units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMA5D27B-CUR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMA5D27B-CUR part is unused and in its original packaging.
Return procedure for ATSAMA5D27B-CUR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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