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Microchip Technology ATSAMA5D27C-D5M-CUR
- Part No.:
- ATSAMA5D27C-D5M-CUR
- Manufacturer:
- Microchip Technology
- Category:
- Microprocessors
- Package:
- 289-LFBGA
- Datasheet:
-
ATSAMA5D27C-D5M-CUR.pdf
- Description:
- IC MPU SAMA5D2 500MHZ 289LFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:2,455
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Product details
Overview
ATSAMA5D27C-D5M-CUR from Microchip Technology is a System-in-Package (SiP) microprocessor unit integrating an Arm® Cortex®-A5 core (up to 500 MHz), TrustZone® security, NEON™ media engine, and 2 Gbit LPDDR2-SDRAM in a single TFBGA361 package. It delivers high-bandwidth memory access via a 32-bit DDR controller with on-the-fly AES encryption/decryption, supports Linux® OS deployments, and targets industrial HMI, secure edge gateways, and embedded vision systems.
For engineers reviewing the ATSAMA5D27C-D5M-CUR datasheet, ATSAMA5D27C-D5M-CUR pinout, ATSAMA5D27C-D5M-CUR application, or ATSAMA5D27C-D5M-CUR equivalent, key selection criteria include LPDDR2-SDRAM capacity (2 Gbit), 361-ball TFBGA package compatibility, integrated security features (AESB, SHA256, tamper detection), and peripheral support for ISC (5-Mpixel camera), GMAC (10/100 Ethernet AVB), and dual CAN-FD controllers.
Technical Context
The ATSAMA5D27C-D5M-CUR implements a dual-bank, 32-bit LPDDR2-SDRAM interface compliant with JEDEC LPDDR2-S4B, supporting 1.8 V (VDD18) and 1.2 V (VDD12) supplies, RL=3/WL=1 timing, and deep power-down modes. Its memory controller includes hardware-based AES encryption/decryption and partial array self-refresh (PASR) for energy-efficient operation.
It integrates a full-featured Arm Cortex-A5 processor with MMU, 32-Kbyte L1 I/D caches, configurable 128-Kbyte L2 cache, and dedicated security peripherals including Integrity Check Monitor (ICM), 5-Kbyte scrambled SRAM with tamper response, and 256-bit scrambled registers - all operating within -40°C to +85°C ambient conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-A5 @ up to 500 MHz with ARMv7-A, TrustZone®, NEON™, ETM/ETB |
| Integrated Memory | 2 Gbit LPDDR2-SDRAM (8 Mwords × 8 Banks × 32 bits), JEDEC S4B-compliant |
| Memory Interface | 32-bit DDR multiport controller with on-the-fly AESB encryption/decryption path |
| Package | TFBGA361, 0.8 mm pitch, 16 mm × 16 mm footprint |
| Operating Temp | -40°C to +85°C ambient, qualified for industrial applications |
| Security Features | AES-128/192/256, SHA-1/224/256/384/512, TRNG, ICM (SHA256), 8 tamper pins |
| Peripherals | GMAC (10/100 w/ IEEE 802.1AS/1588), ISC (5-Mpixel parallel sensor), dual MCAN-FD, LCD TFT (24-bit RGB) |
Pinout & Package
ATSAMA5D27C-D5M-CUR is housed in a 361-ball Thin Fine-Pitch Ball Grid Array (TFBGA361) package with 0.8 mm ball pitch and 16 mm × 16 mm body size. Power rails include DDRM_VDD18 (1.7–1.9 V), DDRM_VDD12 (1.14–1.3 V), VDDIOP0/VDDIOP1 (1.8 V), and VDDSDMMC (1.8 V). The ballout is identical to other 1 Gbit/2 Gbit LPDDR2-based SAMA5D27 variants per DS60001484D Table 6-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDM_VDD18 | LPDDR2 Core Supply | 1.7–1.9 V supply for LPDDR2 memory core; requires tight regulation and decoupling |
| VDDM_VDD12 | LPDDR2 I/O Supply | 1.14–1.3 V supply for LPDDR2 I/O; HSUL_12 interface compliance |
| CLK / CLKN | Differential Clock Input | LVDS-compatible differential clock pair for LPDDR2 timing reference (RL=3, WL=1) |
| DQS / DQSN | Differential Data Strobe | Edge-aligned with read data, center-aligned with write data; critical for DDR timing margin |
| DM[7:0] | Data Mask | Byte-level write masking for LPDDR2; enables precise partial writes without read-modify-write |
Key Features
| Feature | Design Value |
|---|---|
| LPDDR2 Integration | 2 Gbit density eliminates external memory routing, reduces PCB layers, and improves signal integrity for high-speed DDR paths |
| On-the-fly AES Encryption | Hardware-accelerated AESB engine encrypts/decrypts LPDDR2 traffic in real time-no software overhead or latency penalty |
| Partial Array Self-Refresh (PASR) | Reduces LPDDR2 self-refresh power by up to 40% by refreshing only active memory banks during low-power modes |
| Secure Boot & Tamper Response | 5-Kbyte scrambled SRAM with 1-Kbyte non-erasable region on tamper detection; 8 configurable tamper pins with dynamic monitoring |
| Industrial Temperature Range | Full functionality guaranteed from -40°C to +85°C, validated for extended-life embedded deployments |
Applications
| Industrial HMI | Secure Edge Gateway |
|---|---|
Use Scenario: Touch-enabled factory operator panel with real-time diagnostics and firmware update capability. IC Role / Device Role / Timing Role: Main application processor executing Linux® with Qt-based GUI, driving 1024×768 TFT display and 8×8 capacitive PTC. Use Value: Integrated 2 Gbit LPDDR2 eliminates memory layout complexity; AESB ensures encrypted OTA updates; ISC supports optional barcode scanner integration. | Use Scenario: Field-deployed IIoT gateway aggregating Modbus, CAN, and Ethernet data with TLS-secured cloud upload. IC Role / Device Role / Timing Role: Secure network host running Yocto Linux, managing dual MCAN-FD buses, GMAC with IEEE 1588 timestamping, and hardware crypto acceleration. Use Value: TrustZone® isolates secure boot and TLS stack; PASR extends battery life in solar-powered deployments; tamper pins detect physical intrusion attempts. |
| Embedded Vision Node | Medical Device Controller |
Use Scenario: Portable ultrasound probe with raw Bayer image capture and real-time edge processing. IC Role / Device Role / Timing Role: Image Sensor Controller (ISC) master interfacing 5-Mpixel parallel sensor; Cortex-A5 runs lightweight inference model on ARM NEON™. Use Value: Direct LPDDR2 connection enables high-throughput sensor streaming (≥100 MB/s); 128-Kbyte L2 cache optimizes frame buffering; low-power backup mode preserves state during brief power loss. | Use Scenario: FDA-classified patient monitor requiring data integrity, audit logging, and anti-tampering safeguards. IC Role / Device Role / Timing Role: Safety-critical controller executing certified RTOS, validating sensor inputs via ADC (12-bit, 12-channel), and enforcing secure boot chain. Use Value: ICM (SHA256) verifies firmware authenticity at boot; scrambled SRAM stores cryptographic keys; RTC timestamps security events for regulatory traceability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMA5D27C-D1G-CUR | 1 Gbit DDR2-SDRAM (not LPDDR2); TFBGA289 package; lower memory bandwidth and power efficiency | Suitable for smaller Linux® images or real-time OS; lacks LPDDR2 low-power features (PASR, ATCSR) | Select when cost-sensitive designs prioritize DDR2 compatibility over LPDDR2 power savings and density |
| ATSAMA5D28C-LD2G-CUR | Same 2 Gbit LPDDR2 and TFBGA361, but adds environmental monitors (temp/voltage/frequency) and die shield | Required for safety-critical or high-reliability applications needing runtime health telemetry and active shielding | Select when NDA-accessible environmental monitoring and enhanced physical security are mandatory |
Compared with ATSAMA5D27C-D1G-CUR, the ATSAMA5D27C-D5M-CUR provides higher memory bandwidth and deeper power savings via LPDDR2-specific features; compared with ATSAMA5D28C-LD2G-CUR, it omits environmental monitors and die shield-reducing cost while retaining full security and vision capabilities.
Availability
ATSAMA5D27C-D5M-CUR is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateways, and embedded vision applications requiring stable component supply, long-term lifecycle support, and qualified industrial temperature performance.
Supply support for ATSAMA5D27C-D5M-CUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, FPGAs, and security solutions, serving industrial, automotive, communications, and consumer markets with vertically integrated silicon and software.
The SAMA5D2 product line delivers secure, low-power Arm Cortex-A5 MPUs optimized for Linux-capable embedded applications-emphasizing hardware-enforced security, memory integration, and industrial-grade reliability.
FAQ
What memory type and capacity does the ATSAMA5D27C-D5M-CUR integrate?
The ATSAMA5D27C-D5M-CUR integrates 2 Gbit LPDDR2-SDRAM (8 Mwords × 8 Banks × 32 bits) in a single SiP package. This memory is JEDEC LPDDR2-S4B compliant, operates at 1.7–1.9 V (VDD18) and 1.14–1.3 V (VDD12), and interfaces via a dedicated 32-bit DDR controller with on-the-fly AES encryption/decryption. No external memory components are required for basic operation.
Is the ATSAMA5D27C-D5M-CUR pin-compatible with other SAMA5D2 SIP variants?
No-ATSAMA5D27C-D5M-CUR uses the 361-ball TFBGA package, which is not pin-to-pin compatible with 196-ball or 289-ball SAMA5D2 SIP variants. Per DS60001484D Section 6, the 361-ball ballout is shared only among LPDDR2-based SAMA5D27 and SAMA5D28 devices (e.g., ATSAMA5D27C-LD2G-CUR, ATSAMA5D28C-LD2G-CUR). DDR2-based variants use different ballouts and power domains.
Does the ATSAMA5D27C-D5M-CUR support secure boot and runtime security features?
Yes. The ATSAMA5D27C-D5M-CUR includes a secure boot loader in masked ROM, hardware-accelerated AES/SHA/TRNG engines, Integrity Check Monitor (ICM) using SHA256, 5-Kbyte scrambled SRAM with tamper-triggered erasure, and up to eight configurable tamper pins. These features enable root-of-trust establishment, firmware authentication, and physical intrusion detection-all enforced before and during ATSAMA5D27C-D5M-CUR execution.
What camera interfaces does the ATSAMA5D27C-D5M-CUR support?
The ATSAMA5D27C-D5M-CUR includes a dedicated Image Sensor Controller (ISC) supporting parallel 12-bit interfaces for Raw Bayer, YCbCr, Monochrome, and JPEG-compressed sensors up to 5 megapixels. It accepts ITU-R BT.601/656/1120 timing, provides pixel clock generation, and connects directly to LPDDR2 for high-throughput frame buffering-enabling real-time vision processing without external FIFOs or bridge ICs.
What industrial networking features are built into the ATSAMA5D27C-D5M-CUR?
The ATSAMA5D27C-D5M-CUR integrates a 10/100 Ethernet MAC (GMAC) with IEEE 802.1AS time synchronization, IEEE 1588 Precision Time Protocol (PTP) hardware timestamping, and IEEE 802.1Qav credit-based traffic shaping. It also includes two MCAN-FD controllers supporting time- and event-triggered transmission-making ATSAMA5D27C-D5M-CUR suitable for deterministic industrial networks like PROFINET, EtherCAT (via software stack), and time-sensitive TSN edge nodes.
ATSAMA5D27C-D5M-CUR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- 289-LFBGA
- Series:
- SAMA5D2
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A5
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 500MHz
- Co-Processors/DSP:
- Multimedia; NEON™ MPE
- RAM Controllers:
- LPDDR1, LPDDR2, LPDDR3, DDR2, DDR3, DDR3L, QSPI
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- Keyboard, LCD, Touchscreen
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 + HSIC
- Voltage - I/O:
- 3.3V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ, Boot Security, Cryptography, RTIC, Secure Fusebox, Secure JTAG, Secure Memory, Secure RTC
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 289-LFBGA (14x14)
- Additional Interfaces:
- I2C, SMC, SPI, UART, USART, QSPI
ATSAMA5D27C-D5M-CUR FAQ
1.How can I place an order for ATSAMA5D27C-D5M-CUR through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMA5D27C-D5M-CUR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMA5D27C-D5M-CUR reliable?
The price and inventory of ATSAMA5D27C-D5M-CUR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMA5D27C-D5M-CUR is usually 5 days.
3.What payment methods are accepted for ATSAMA5D27C-D5M-CUR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMA5D27C-D5M-CUR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMA5D27C-D5M-CUR?
ATSAMA5D27C-D5M-CUR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMA5D27C-D5M-CUR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMA5D27C-D5M-CUR?
For technical support, including ATSAMA5D27C-D5M-CUR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMA5D27C-D5M-CUR requirements.
6.How does Aetrix verify that ATSAMA5D27C-D5M-CUR is sourced from the original manufacturer or authorized distributors?
All ATSAMA5D27C-D5M-CUR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMA5D27C-D5M-CUR meets industry standards.
7.What is the process for return or replacement of ATSAMA5D27C-D5M-CUR?
All ATSAMA5D27C-D5M-CUR units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMA5D27C-D5M-CUR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMA5D27C-D5M-CUR part is unused and in its original packaging.
Return procedure for ATSAMA5D27C-D5M-CUR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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