Microchip Technology ATSAMA5D27C-LD2G-CU

Overview

ATSAMA5D27C-LD2G-CU from Microchip Technology is a System-in-Package (SIP) MPU integrating an Arm® Cortex®-A5 core (up to 500 MHz), TrustZone® security, NEON™ media engine, and 2 Gbit LPDDR2-SDRAM in a single TFBGA361 package. It delivers high-bandwidth memory access with on-the-fly AES encryption/decryption and supports Linux®-based industrial HMI and edge gateway applications.

For engineers reviewing the ATSAMA5D27C-LD2G-CU datasheet, ATSAMA5D27C-LD2G-CU pinout, ATSAMA5D27C-LD2G-CU application, or ATSAMA5D27C-LD2G-CU equivalent, key selection considerations include LPDDR2-SDRAM integration, 128 I/Os with peripheral multiplexing, dual CAN-FD controllers, GMAC with IEEE 1588 PTP, and hardware crypto acceleration (AES-256, SHA-512, TRNG).

Technical Context

The ATSAMA5D27C-LD2G-CU implements a 32-bit Armv7-A architecture with MMU, 32-Kbyte L1 instruction/data caches, and configurable 128-Kbyte L2 cache usable as internal SRAM. Its memory subsystem features a 32-bit scramblable DDR controller supporting AP Memory LPDDR2-SDRAM up to 2 Gb at 1.8 V (VDD18) and 1.2 V (VDD12) supplies, with JEDEC LPDDR2-S4B compliance, PASR, ATCSR, and Deep Power-Down mode.

Security is enforced via Secure Boot Loader, 5 Kbytes of tamper-responsive scrambled SRAM, eight tamper pins, Integrity Check Monitor (SHA256), and hardware-accelerated cryptography including AESB for on-the-fly memory encryption. Low-power operation includes Ultra-Low-Power mode with fast wake-up and Extended Backup mode with LPDDR2 in Self-Refresh.

Key Specifications

Pinout & Package

ATSAMA5D27C-LD2G-CU is housed in a 361-ball Thin Fine-Pitch Ball Grid Array (TFBGA361) package with 0.8 mm ball pitch and 16 mm × 16 mm footprint. The package supports LPDDR2-SDRAM integration and provides dedicated power rails (VDDM_VDD18, VDDM_VDD12) and signal integrity–optimized ballout per DS60001484D.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar MPU applications.

Compared with ATSAMA5D27C-LD2G-CU, the ATSAMA5D28C-LD2G-CU adds certified environmental monitoring for safety-critical use, while ATSAMA5D27C-D1G-CU trades LPDDR2's low-power advantage for DDR2's broader vendor support and lower-cost PCB stackup.

Availability

ATSAMA5D27C-LD2G-CU is available at Aetrix Electronics and suitable for industrial HMI, edge gateways, medical imaging terminals, and secure IoT appliances requiring stable component supply across long product lifecycles.

Supply support for ATSAMA5D27C-LD2G-CU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a leading provider of microcontrollers, analog, FPGA, and security solutions, with a focus on industrial, automotive, and communications markets.

The SAMA5D2 SIP product line integrates Arm Cortex-A5 MPUs with high-density DRAM to simplify board design, reduce EMI sensitivity, and accelerate secure Linux-based embedded development for resource-constrained edge applications.

FAQ

What memory types does the ATSAMA5D27C-LD2G-CU support?

The ATSAMA5D27C-LD2G-CU integrates 2 Gbit LPDDR2-SDRAM and supports no external memory interface beyond its built-in SIP configuration. It does not support DDR2, DDR3, or LPDDR3. The LPDDR2 interface complies with JEDEC LPDDR2-S4B, operates at 1.7–1.9 V (VDD18) and 1.14–1.3 V (VDD12), and includes features like Partial Array Self-Refresh and Auto Temperature Compensated Self-Refresh. ATSAMA5D27C-LD2G-CU relies entirely on this integrated memory for system operation.

Does the ATSAMA5D27C-LD2G-CU support CAN FD communication?

Yes, the ATSAMA5D27C-LD2G-CU includes two host CAN-FD (MCAN) controllers with SRAM-based mailboxes and time- and event-triggered transmission. However, Microchip explicitly states that MCAN implements the non-ISO CAN FD frame format and does not pass the ISO 16845-1:2016 CAN FD Conformance Test. ATSAMA5D27C-LD2G-CU is suitable for proprietary or non-ISO-compliant CAN FD networks but not for applications requiring strict ISO FD interoperability.

What security features are implemented in hardware on the ATSAMA5D27C-LD2G-CU?

The ATSAMA5D27C-LD2G-CU includes hardware-enforced security features: Secure Boot Loader, 5 Kbytes of tamper-responsive scrambled SRAM (1 Kbyte non-erasable on intrusion), eight configurable tamper pins, Integrity Check Monitor (SHA256), and full hardware crypto accelerators for AES-256/192/128, SHA-1/224/256/384/512, TDES, and NIST SP 800-22–compliant TRNG. ATSAMA5D27C-LD2G-CU also supports on-the-fly AES encryption/decryption of LPDDR2 traffic via the AESB module.

Is the ATSAMA5D27C-LD2G-CU pin-compatible with other SAMA5D2 SIP variants?

No, the ATSAMA5D27C-LD2G-CU is not pin-compatible with other SAMA5D2 SIP variants. It uses the 361-ball TFBGA361 package, while DDR2-based variants (e.g., ATSAMA5D27C-D1G-CU) use TFBGA289. Microchip explicitly states "SAMA5D2 DDR2 SIP devices are not pin-to-pin compatible with SAMA5D2 devices." ATSAMA5D27C-LD2G-CU has a unique ballout optimized for LPDDR2 signaling, including dedicated VDD18/VDD12 rails and differential strobes not present in DDR2 variants.

What operating systems are supported on the ATSAMA5D27C-LD2G-CU?

The ATSAMA5D27C-LD2G-CU is validated for Linux® distributions including Yocto Project–based builds and Buildroot, leveraging its 2 Gbit LPDDR2 capacity and Arm Cortex-A5 architecture. It also supports bare-metal and real-time OS deployments (e.g., FreeRTOS) for applications requiring deterministic latency. Microchip provides BSPs, device trees, and kernel patches specifically for ATSAMA5D27C-LD2G-CU. Smaller memory configurations (e.g., 128 Mbit DDR2) target bare-metal use, but ATSAMA5D27C-LD2G-CU's 2 Gbit LPDDR2 is sized for full Linux stacks.