Microchip Technology ATSAMA5D28B-CU

Overview

ATSAMA5D28B-CU from Microchip Technology is a high-performance, ultra-low-power 32-bit ARM Cortex-A5 microprocessor running at up to 500 MHz, integrating DDR3/DDR3L/LPDDR3 memory controllers, dual CAN-FD interfaces, 12-channel 12-bit ADC with resistive touchscreen support, and hardware-accelerated AES/SHA/TRNG crypto engines. It features ARM TrustZone security, 128 KB L2 cache configurable as SRAM, and 5 KB tamper-protected secure SRAM - deployed in industrial HMI, secure IoT gateways, and point-of-sale terminals.

For engineers reviewing the ATSAMA5D28B-CU datasheet, ATSAMA5D28B-CU pinout, ATSAMA5D28B-CU application, or ATSAMA5D28B-CU equivalent, key selection considerations include its 289-ball LFBGA package, dual QSPI interfaces, 8-tamper-pin capability, IEEE 1588 PTP support in GMAC, and verified compatibility with Linux BSPs and bare-metal C examples provided by Microchip.

Technical Context

The ATSAMA5D28B-CU implements a multilayer AXI/AHB bus matrix with two 16-channel XDMAC controllers, enabling zero-overhead peripheral-to-memory transfers for camera (ISC), audio (I2SC/SSC/Class D), and networking (GMAC/USB) subsystems. Its security architecture combines ARM TrustZone-enforced world separation, hardware-scrambled memories (DDR/QSPI/SRAM), and Integrity Check Monitor (ICM) using SHA256 to detect runtime memory corruption.

Power management includes three software-selectable low-power modes: Ultra-low-power mode with SleepWalking™ for partial asynchronous wakeup, Backup mode with RTC and 5 KB SRAM retention, and extended Backup with DDR self-refresh. The device supports on-the-fly AES encryption/decryption for DDR and QSPI via dedicated AESB bridge, and includes environmental monitors (temperature/voltage/frequency) and active die shield - confirmed for SAMA5D28 variants per Microchip document 44036.

Key Specifications

Pinout & Package

ATSAMA5D28B-CU is housed in a 289-ball Low-Profile Fine-Pitch Ball Grid Array (LFBGA) package with 14 mm × 14 mm body size and 0.8 mm ball pitch. This package supports high-density routing for DDR3, QSPI, and multiple high-speed peripherals while meeting industrial thermal and mechanical reliability requirements.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-security ARM Cortex-A5 MPU applications.

Compared with ATSAMA5D27B-CU and i.MX6ULL, the ATSAMA5D28B-CU delivers deeper hardware-rooted security (tamper pins, die shield, ICM), tighter integration of vision/audio/peripheral subsystems, and lower power in ultra-low-power modes - making it optimal for certified secure edge devices where physical attack resistance is mandatory.

Availability

ATSAMA5D28B-CU is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, and point-of-sale terminals requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for safety-critical deployments.

Supply support for ATSAMA5D28B-CU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology is a global semiconductor company specializing in microcontrollers, analog, FPGA, and security solutions, with strong focus on industrial, automotive, and aerospace applications.

The SAMA5D2 series was designed specifically for secure, low-power, high-performance embedded applications - targeting industrial automation, IoT edge nodes, and payment systems requiring hardware-enforced trust and long-term reliability.

FAQ

What is the maximum operating frequency of the ATSAMA5D28B-CU?

The ATSAMA5D28B-CU operates at up to 500 MHz on its ARM Cortex-A5 core, with system clocks running up to 166 MHz under typical conditions. This frequency is supported across industrial temperature ranges (-40°C to +85°C) and validated with DDR3 memory interfaces and peripheral subsystems fully enabled. The ATSAMA5D28B-CU achieves this performance while maintaining ultra-low-power operation through dynamic voltage and frequency scaling managed by its integrated PMC.

Does the ATSAMA5D28B-CU support secure boot with hardware root-of-trust?

Yes, the ATSAMA5D28B-CU implements a hardware-enforced secure boot process using a maskable 64-Kbyte ROM containing a secure boot loader, TrustZone isolation, and hardware cryptographic accelerators (AES/SHA/TRNG). It verifies signature authenticity and image integrity before execution, and supports encrypted code loading from QSPI or DDR via on-the-fly AESB decryption. This architecture forms the hardware root-of-trust for ATSAMA5D28B-CU-based systems.

What package type and pin count does the ATSAMA5D28B-CU use?

The ATSAMA5D28B-CU is packaged in a 289-ball Low-Profile Fine-Pitch Ball Grid Array (LFBGA) with 14 mm × 14 mm body size and 0.8 mm ball pitch. This package provides 128 user-configurable I/Os and is optimized for high-speed DDR3 routing, thermal dissipation, and industrial board-level reliability. Pin compatibility is documented in Microchip's DS60001476B, specifically Table 6-4 for SAMA5D28B/C variants.

How many tamper detection pins does the ATSAMA5D28B-CU have, and what happens on detection?

The ATSAMA5D28B-CU includes eight dedicated tamper detection pins (PIOBU[0:7]) supporting both static and dynamic intrusion monitoring. Upon tamper event detection, the device immediately erases 4 KB of secure SRAM, logs a timestamped record in the secure RTC, and can generate an interrupt or system reset. These features are confirmed for the SAMA5D28 variant in Microchip document 44036 and are integral to its IEC 60730 Class B and physical security certification path.

Which memory types are supported by the ATSAMA5D28B-CU's integrated controllers?

The ATSAMA5D28B-CU supports DDR2, DDR3, DDR3L, LPDDR1, LPDDR2, and LPDDR3 via its 32-bit multiport DDR controller, and SLC/MLC NAND Flash with up to 32-bit PMECC error correction. It also integrates two QSPI controllers for serial NOR Flash and one 128-Kbyte scrambled internal SRAM. All external memories - including DDR and QSPI - are protected by on-the-fly AES encryption/decryption and SHA256-based integrity checking via the ICM, as specified for ATSAMA5D28B-CU in DS60001476B.