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Microchip Technology ATSAMA5D28B-CUR
- Part No.:
- ATSAMA5D28B-CUR
- Manufacturer:
- Microchip Technology
- Category:
- Microprocessors
- Package:
- 289-LFBGA
- Datasheet:
-
ATSAMA5D28B-CUR.pdf
- Description:
- IC MPU SAMA5D2 500MHZ 289LFBGA
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
ATSAMA5D28B-CUR from Microchip Technology is a high-performance, ultra-low-power ARM® Cortex®-A5 microprocessor unit (MPU) operating up to 500 MHz, integrating 128 KB L2 cache configurable as SRAM, 128 KB scrambled internal SRAM, 160 KB ROM with secure boot loader, and hardware crypto-accelerators for AES-256, SHA-512, and TRNG. It supports DDR3L/LPDDR3 memory, dual QSPI, two CAN-FD controllers, 10/100 Ethernet MAC with AVB/PTP, and 8 tamper detection pins - deployed in industrial IoT gateways requiring secure edge processing and real-time connectivity.
For engineers reviewing the ATSAMA5D28B-CUR datasheet, ATSAMA5D28B-CUR pinout, ATSAMA5D28B-CUR application, or ATSAMA5D28B-CUR equivalent, key selection considerations include its 289-ball LFBGA package, TrustZone-enabled secure boot, on-the-fly AESB encryption for DDR/QSPI, 12-channel 12-bit ADC with resistive touchscreen support, and dual USB high-speed ports (host/device + HSIC).
Technical Context
The ATSAMA5D28B-CUR implements a multilayer bus architecture with two 16-channel 64-bit XDMAC controllers and dedicated peripheral DMAs to sustain high-bandwidth data transfers without CPU overhead. Its memory subsystem includes a 16-bit or 32-bit DDR controller supporting DDR2/DDR3/DDR3L/LPDDR1–3 with on-the-fly scrambling and AESB encryption-decryption paths.
Security is enforced via ARM TrustZone partitioning, a Secure Advanced Interrupt Controller (SAIC), Integrity Check Monitor (ICM) using SHA-256, 5 KB tamper-responsive scrambled SRAM (1 KB non-erasable), and a programmable 544-bit fuse box with JTAG protection. The device features three low-power modes - Idle, Ultra-low-power (with SleepWalking™), and Backup - with RTC and wakeup logic active in Backup mode and optional DDR self-refresh extension.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-A5 @ up to 500 MHz, NEON SIMD, VFPv4 FPU, TrustZone security extension |
| Memory Architecture | 32 KB L1 I/D cache, 128 KB configurable L2 cache/SRAM, 128 KB scrambled SRAM, 160 KB ROM with secure boot loader |
| DDR Interface | 16/32-bit multiport DDR controller supporting DDR2/DDR3/DDR3L/LPDDR1–3 up to 512 MB, DLL-off only for DDR3/DDR3L |
| Crypto Acceleration | AES-128/192/256, SHA-1/224/256/384/512, TDES, TRNG compliant with NIST SP 800-22 and FIPS 140-2/140-3 |
| Peripherals | 1× 10/100 EMAC with IEEE 802.1AS/1Qav/1588, 2× CAN-FD, 2× QSPI, 2× SDMMC (SD 3.0/eMMC 4.51 + SD 2.0/eMMC 4.41), 8× UART/FLEXCOM, 12× ADC inputs |
| Security Features | ARM TrustZone, ICM (SHA-256), 8 tamper pins, 256-bit scrambled registers, secure fuse box, on-the-fly AESB for DDR/QSPI |
| Package | 289-ball LFBGA, 14 × 14 mm body, 0.8 mm pitch, RoHS-compliant |
Pinout & Package
ATSAMA5D28B-CUR is housed in a 289-ball Low-Profile Fine-Pitch Ball Grid Array (LFBGA) package with 0.8 mm ball pitch and 14 mm × 14 mm body size. This package supports high-density routing and thermal performance suitable for industrial embedded applications requiring long-term reliability and extended temperature operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDIO / VDDCORE / VDDANA / VDDBU | Power Supply Rails | Dedicated voltage domains for I/O (3.3 V), core logic (1.05–1.2 V), analog (1.8 V), and backup (1.2 V); enable independent power management and low-power retention |
| DDR_D[31:0], DDR_A[13:0], DDR_BA[2:0] | DDR Memory Interface | 32-bit data bus, 14-bit address, 3-bit bank select - supports high-throughput external memory access with configurable timing and calibration |
| PA0–PA31, PB0–PB31, PC0–PC31, PD0–PD31 | Programmable I/O Lines | Up to 128 multiplexed GPIOs; each supports up to 8 peripheral functions, synchronous 32-bit write capability, and individual pull-up/pull-down control |
| QSPI0_SCK/CS/IO[0:3], QSPI1_SCK/CS/IO[0:3] | Quad SPI Interfaces | Dual independent QSPI controllers enabling fast, secure code/data fetch from encrypted flash; IO[0:3] support quad/dual/single-line modes with configurable drive strength |
| CANRX0/CANTX0, CANRX1/CANTX1 | CAN-FD Controllers | Two fully compliant CAN-FD interfaces with SRAM-based mailboxes, time-triggered transmission, and event-triggered wakeup - critical for deterministic industrial fieldbus communication |
| GMAC_GTX[0:3]/GRX[0:3], GMDC/GMDIO | Ethernet MAC Interface | 10/100 Mbps PHY interface with IEEE 802.1AS timestamping, credit-based shaping (802.1Qav), and PTP hardware acceleration for synchronized networked systems |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone-secured boot and runtime isolation | Enables hardware-enforced separation of secure/non-secure worlds for firmware integrity, secure key storage, and protected peripheral access |
| On-the-fly AESB encryption/decryption | Hardware-accelerated AES-128/192/256 applied transparently to DDR and QSPI memory traffic - no software overhead, zero latency penalty |
| 8-pin tamper detection with dynamic monitoring | Configurable static/dynamic intrusion sensing; triggers immediate erasure of 4 KB secure SRAM and 256-bit registers upon violation |
| Integrated Integrity Check Monitor (ICM) | SHA-256-based hardware monitor verifying integrity of all internal/external memories (DDR, QSPI, SMC) - detects unauthorized modification in real time |
| SleepWalking™ low-power peripheral autonomy | Allows peripherals (ADC, timers, comparators) to operate and generate events in Ultra-low-power mode without waking CPU - extends battery life in sensor-edge nodes |
Applications
| Industrial IoT Gateway | Secure Point-of-Sale Terminal |
|---|---|
Use Scenario: Aggregating and preprocessing sensor data from Modbus/KNX field devices while forwarding encrypted telemetry to cloud platforms via LTE/Wi-Fi. IC Role / Device Role / Timing Role: Central MPU executing Linux-based edge AI inference, managing dual CAN-FD buses, 10/100 Ethernet with PTP synchronization, and secure TLS offload via crypto engines. Use Value: Combines deterministic real-time I/O (CAN-FD, timers), hardware-accelerated encryption (AESB, SHA-512), and TrustZone-protected secure boot - eliminating need for external security co-processors. | Use Scenario: Payment terminal handling EMV chip card transactions, PIN entry, and contactless NFC, requiring PCI PTS v6 compliance and anti-tampering certification. IC Role / Device Role / Timing Role: Root-of-trust MPU running certified secure OS, validating firmware signatures, encrypting cardholder data in scrambled SRAM, and enforcing tamper-response protocols. Use Value: Integrates 8 tamper pins, 5 KB secure SRAM with non-erasable 1 KB region, secure fuse box, and ICM - meeting PCI PTS physical security requirements without discrete security ICs. |
| Medical Edge Analytics Device | Smart Energy Meter with HAN Interface |
Use Scenario: Portable ultrasound or ECG analyzer performing real-time signal processing, local display rendering, and HIPAA-compliant data export over Wi-Fi/Ethernet. IC Role / Device Role / Timing Role: High-throughput MPU driving LCD TFT controller (1024×768), ISC image sensor interface, stereo Class D audio, and 12-bit ADC with resistive touchscreen overlay. Use Value: Delivers NEON-accelerated DSP, hardware alpha blending, and on-chip 128 KB L2 cache - enabling smooth UI rendering and low-latency waveform analysis without external graphics memory. | Use Scenario: Two-way smart meter communicating with utility grid (via PLC or RF) and home area network (HAN) using Zigbee/Thread, while logging consumption with tamper-proof timestamps. IC Role / Device Role / Timing Role: Dual-role communications hub managing IEEE 802.15.4 radio stack, 10/100 Ethernet with AVB/PTP, RTC with intrusion timestamping, and environmental monitors (temp/voltage/frequency). Use Value: Leverages integrated PTP hardware, secure RTC with tamper logging, and environmental sensors (SAMA5D28-specific) - satisfying ANSI C12.22 and DLMS/COSEM security mandates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-security, low-power ARM Cortex-A5 MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMA5D27C-CUR | 256-ball TFBGA, 8×8 mm, 0.4 mm pitch; supports same core/peripherals but lacks environmental monitors and die shield; 6 tamper pins vs. 8 | Targeted at space-constrained designs where thermal monitoring and advanced physical security are not required | Select when footprint reduction and cost optimization outweigh need for die-level tamper detection and environmental sensing |
| i.MX6ULL | ARM Cortex-A7 @ 900 MHz; no TrustZone-enforced secure boot; software-only crypto acceleration; no integrated tamper pins or ICM | Used in cost-sensitive consumer HMI and basic gateway applications lacking regulatory security mandates | Choose only if design does not require hardware-rooted trust, on-the-fly memory encryption, or IEC 60730 Class B safety certification |
Compared with ATSAMA5D28B-CUR, ATSAMA5D27C-CUR offers identical functional capability in a smaller package but omits environmental monitors and reduces tamper pin count; i.MX6ULL delivers higher clock speed but lacks hardware security primitives essential for PCI PTS or IEC 60730 Class B compliance.
Availability
ATSAMA5D28B-CUR is available at Aetrix Electronics and suitable for industrial IoT gateways, secure point-of-sale terminals, and medical edge analytics devices requiring stable component supply, long lifecycle support, and traceable sourcing.
Supply support for ATSAMA5D28B-CUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company delivering microcontrollers, analog, FPGA, and security solutions with emphasis on reliability, longevity, and embedded system integration.
The SAMA5D2 product line is designed for secure, low-power industrial and IoT edge applications demanding hardware-enforced trust, real-time connectivity, and cryptographic acceleration - targeting markets where safety certification (IEC 60730 Class B) and security compliance (PCI PTS, FIPS) are mandatory.
FAQ
What is the primary security architecture of the ATSAMA5D28B-CUR?
The ATSAMA5D28B-CUR implements a layered hardware security architecture anchored by ARM TrustZone, which partitions secure and non-secure execution environments. It integrates an Integrity Check Monitor (ICM) using SHA-256 to verify memory integrity, 8 dedicated tamper detection pins with configurable response (including immediate erasure of 4 KB secure SRAM), a 544-bit programmable fuse box for JTAG lockdown, and on-the-fly AESB encryption for DDR and QSPI memory. These features collectively meet requirements for PCI PTS v6 and IEC 60730 Class B certification.
Does the ATSAMA5D28B-CUR support IEEE 1588 Precision Time Protocol?
Yes, the ATSAMA5D28B-CUR includes full hardware acceleration for IEEE 1588 Precision Time Protocol (PTP) within its 10/100 Ethernet MAC (GMAC). It supports hardware timestamping of ingress/egress frames, IEEE 802.1AS time synchronization, and credit-based traffic shaping per IEEE 802.1Qav - enabling sub-microsecond time coordination across distributed industrial networks without CPU intervention.
What memory types and interfaces does the ATSAMA5D28B-CUR support?
The ATSAMA5D28B-CUR supports DDR2, DDR3, DDR3L, LPDDR1, LPDDR2, and LPDDR3 via its high-bandwidth 16/32-bit DDR controller (DLL-off only for DDR3/DDR3L), up to 512 MB. It also integrates an 8-bit SLC/MLC NAND controller with up to 32-bit PMECC, two QSPI interfaces for encrypted flash, and two SDMMC hosts (SD 3.0/eMMC 4.51 and SD 2.0/eMMC 4.41). Internal memory includes 128 KB scrambled SRAM, 160 KB ROM with secure boot loader, and 128 KB configurable L2 cache.
How many CAN-FD interfaces does the ATSAMA5D28B-CUR provide, and what are their capabilities?
The ATSAMA5D28B-CUR provides two fully compliant CAN-FD (Controller Area Network with Flexible Data-Rate) controllers. Each supports SRAM-based mailboxes, time-triggered transmission, event-triggered wakeup, and bit rates up to 5 Mbps in the data phase. These interfaces are essential for deterministic, high-integrity communication in automotive diagnostics, industrial automation, and energy grid control systems requiring ISO 11898-1 compliance.
What low-power modes are available on the ATSAMA5D28B-CUR, and how do they differ?
The ATSAMA5D28B-CUR offers three software-selectable low-power modes: Idle (CPU stopped, peripherals active), Ultra-low-power (ULP) Mode 0 (CPU stopped, peripherals clocked at 512 Hz with SleepWalking™ autonomous operation), and ULP Mode 1 (all clocks stopped except wakeup logic). Backup mode retains RTC and wakeup functionality; it can be extended to maintain DDR in self-refresh. These modes enable sub-100 µA standby current while preserving secure state and enabling fast (<10 µs) wakeup from multiple sources including UART, analog comparators, and tamper pins.
ATSAMA5D28B-CUR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- 289-LFBGA
- Series:
- SAMA5D2
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Core Processor:
- ARM® Cortex®-A5
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 500MHz
- Co-Processors/DSP:
- Multimedia; NEON™ MPE
- RAM Controllers:
- LPDDR1, LPDDR2, LPDDR3, DDR2, DDR3, DDR3L, QSPI
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- Keyboard, LCD, Touchscreen
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 + HSIC
- Voltage - I/O:
- 3.3V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ, Boot Security, Cryptography, RTIC, Secure Fusebox, Secure JTAG, Secure Memory, Secure RTC
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 289-LFBGA (14x14)
- Additional Interfaces:
- I2C, SMC, SPI, UART, USART, QSPI
ATSAMA5D28B-CUR FAQ
1.How can I place an order for ATSAMA5D28B-CUR through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMA5D28B-CUR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMA5D28B-CUR reliable?
The price and inventory of ATSAMA5D28B-CUR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMA5D28B-CUR is usually 5 days.
3.What payment methods are accepted for ATSAMA5D28B-CUR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMA5D28B-CUR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMA5D28B-CUR?
ATSAMA5D28B-CUR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMA5D28B-CUR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMA5D28B-CUR?
For technical support, including ATSAMA5D28B-CUR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMA5D28B-CUR requirements.
6.How does Aetrix verify that ATSAMA5D28B-CUR is sourced from the original manufacturer or authorized distributors?
All ATSAMA5D28B-CUR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMA5D28B-CUR meets industry standards.
7.What is the process for return or replacement of ATSAMA5D28B-CUR?
All ATSAMA5D28B-CUR units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMA5D28B-CUR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMA5D28B-CUR part is unused and in its original packaging.
Return procedure for ATSAMA5D28B-CUR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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