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Microchip Technology ATSAMA5D31A-CUR
- Part No.:
- ATSAMA5D31A-CUR
- Manufacturer:
- Microchip Technology
- Category:
- Microprocessors
- Package:
- 324-LFBGA
- Datasheet:
-
ATSAMA5D31A-CUR.pdf
- Description:
- IC MPU SAMA5D3 536MHZ 324LFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:3,892
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Product details
Overview
ATSAMA5D31A-CUR from Microchip Technology (formerly Atmel) is a high-performance, power-efficient ARM® Cortex®-A5 based embedded MPU operating at up to 536 MHz, featuring a VFPv4 floating-point unit, 32 KB instruction and data caches, and integrated security engines (AES-256, SHA-256, TRNG). It supports DDR2/LPDDR2 memory with 24-bit ECC, Gigabit Ethernet with IEEE 1588, dual CAN, LCD controller with overlay acceleration, and 12-channel 12-bit ADC with resistive touchscreen interface - deployed in industrial HMI and battery-powered control panels.
For engineers reviewing the ATSAMA5D31A-CUR datasheet, ATSAMA5D31A-CUR pinout, ATSAMA5D31A-CUR application, or ATSAMA5D31A-CUR equivalent, key selection considerations include its 324-ball LFBGA package, absence of GMAC (unlike SAMA5D33/34/35/36), presence of EMAC and LCDC, dual CAN controllers, and support for secure boot with hardware-accelerated crypto.
Technical Context
The ATSAMA5D31A-CUR implements a multi-layer bus matrix architecture with 39 DMA channels to sustain high-bandwidth data flow between the Cortex-A5 core, DDR2/LPDDR2 memory controller, and peripherals including EMAC, LCDC, and dual CAN. Its memory subsystem includes 160 KB ROM (with boot loader for NAND/eMMC/SD), 128 KB SRAM, and independent static memory controller supporting SLC/MLC NAND with PMECC.
Security is enforced via Atmel Secure Boot, hardware AES/TDES/SHA engines, and TRNG; low-power operation is enabled by shut-down controller, battery-backed registers, and programmable clock gating across domains - all confirmed for this specific variant per Table 1-1 "SAMA5D3 Device Differences".
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-A5 @ 536 MHz with VFPv4 FPU and MMU - enables Linux-capable real-time deterministic execution and floating-point-intensive UI rendering. |
| Memory Interfaces | DDR2/LPDDR2 controller (512 MB, 32-bit, 24-bit ECC); Static Memory Controller with NAND support (SLC/MLC, 24-bit PMECC) - ensures robust external storage for firmware and graphics assets. |
| Peripherals | EMAC (10/100 Mbps), LCDC with alpha-blending/rotation, dual CAN 2.0B controllers (8 mailboxes each), 12-channel 12-bit ADC with touchscreen support - targets wired industrial comms and graphical HMI without external bridge ICs. |
| Security | AES-256/TDES/SHA-256 hardware accelerators, TRNG, Secure Boot - provides root-of-trust for firmware integrity and encrypted OTA updates. |
| Package & I/O | 324-ball LFBGA (15 × 15 mm, 0.8 mm pitch); 160 configurable GPIOs with slew rate control, Schmitt triggers, and per-pin pull-up/down - supports dense PCB layouts with signal integrity control. |
| Power Management | Shut-down controller, battery backup registers, 32 kHz RC oscillator, software-programmable power optimization - enables <0.5 mW low-power mode for battery-operated HMIs. |
Pinout & Package
ATSAMA5D31A-CUR is packaged in a 324-ball Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 15 mm × 15 mm × 1.4 mm, 0.8 mm ball pitch. This package supports high-density routing and thermal dissipation for sustained 536 MHz operation in industrial environments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PA0–PA31 | Parallel I/O Port A | Primary LCD data bus (LCDDAT0–23), PWM outputs, and ISI image sensor interface - enables direct TFT panel driving and camera input without glue logic. |
| PB0–PB17 | Parallel I/O Port B | GMAC physical layer signals (GTX0–7, GRX0–7, GTXCK, GRXCK) - supports full 10/100 Ethernet PHY interfacing with minimal external components. |
| PC0–PC31 | Parallel I/O Port C | EMAC signals (ETX0/1, ERX0/1), SPI1, TWI2, and ADC analog inputs (AD0–AD11) - integrates wired industrial comms and analog sensing on one port. |
| PD0–PD19 | Parallel I/O Port D | MCI0 (eMMC/SD), SPI0, USART0/1, and ADTRG - handles primary boot media and serial debug interfaces with dedicated clock and data lanes. |
| PE0–PE31 | Parallel I/O Port E | External Bus Interface (EBI) address/data lines (A0–A25, D0–D15), NAND control (NANDALE/CLE, NANDRDY) - enables direct connection to NOR/NAND flash and SRAM. |
| DDR_A0–DDR_A13, DDR_D0–DDR_D31 | DDR2/LPDDR2 Interface | Dedicated 32-bit data + 14-bit address + control (DDR_CS, DDR_CKE, DDR_RAS/CAS) - meets JEDEC DDR2 timing requirements with on-die termination calibration (DDR_CALP/N). |
Key Features
| Feature | Design Value |
|---|---|
| ARM Cortex-A5 + VFPv4 | Enables Linux/Yocto deployment with deterministic real-time response and single-precision floating-point performance for UI scaling and image processing. |
| Integrated LCDC with overlays | Hardware-accelerated alpha-blending, rotation, and color space conversion offloads CPU during multi-layer GUI rendering - reduces frame buffer bandwidth by >40%. |
| Dual CAN 2.0B controllers | 8-mailbox per controller with timestamping and FIFO support - satisfies automotive-grade diagnostics and distributed control messaging without external CAN transceivers. |
| Secure Boot + AES/SHA engines | Immutable root-of-trust chain from ROM bootloader through authenticated kernel load; 256-bit AES encryption throughput >100 MB/s - secures firmware against cloning and man-in-the-middle attacks. |
| 12-channel 12-bit ADC with touchscreen | Simultaneous sampling of 4-wire resistive touch coordinates (AD0UL–AD3LR) plus 7 auxiliary analog inputs - eliminates need for external touch controller in HMI designs. |
Applications
| Industrial Control Panel | Smart Energy Gateway |
|---|---|
|
Use Scenario: Touch-enabled operator interface for PLC-based machinery monitoring and parameter configuration in factory automation. IC Role / Device Role / Timing Role: Main application processor executing Linux-based HMI stack, managing LCD display, touchscreen input, and real-time CAN bus communication with field devices. Use Value: Integrated LCDC and dual CAN eliminate external bridge ICs; secure boot ensures firmware authenticity in unattended deployments. |
Use Scenario: DIN-rail mounted gateway aggregating metering data (via RS-485/Modbus) and transmitting securely to cloud via Ethernet/Wi-Fi. IC Role / Device Role / Timing Role: Central host processor running embedded Linux, handling protocol translation, TLS-encrypted Ethernet transport, and local web server for configuration. Use Value: Hardware AES/SHA accelerators enable efficient TLS 1.2 handshake and payload encryption without CPU overhead; EMAC supports deterministic packet timing. |
| Battery-Powered HMI Terminal | Medical Device Display Unit |
|
Use Scenario: Portable diagnostic tool with color TFT display, capacitive/resistive touch, and Bluetooth LE connectivity. IC Role / Device Role / Timing Role: Primary MCU managing display refresh, touch coordinate acquisition, battery monitoring (via ADC), and low-power state transitions. Use Value: Sub-0.5 mW shutdown mode extends battery life; integrated 12-bit ADC with touchscreen support removes external analog front-end. |
Use Scenario: Patient monitor display unit requiring FDA-compliant firmware integrity, ESD-hardened I/O, and high-reliability graphics rendering. IC Role / Device Role / Timing Role: Safety-critical application processor executing certified medical OS, validating boot images cryptographically, and driving high-resolution medical-grade LCD. Use Value: Atmel Secure Boot and tamper-resistant fuse box (192 customer bits) meet IEC 62304 Class C software safety requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar embedded MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMA5D34A-CUR | Includes GMAC (10/100/1000 Mbps) and HSMCI2; lacks EMAC; same LFBGA package and core specs. | Preferred for Gigabit Ethernet backbone nodes; not suitable where 10/100 EMAC + dual CAN + LCDC coexistence is required. | Select only if Gigabit throughput is mandatory and EMAC is unnecessary. |
| NXP i.MX6ULL | ARM Cortex-A7 @ 900 MHz; single CAN; no integrated LCDC; uses external DDR3; different security model (CAAM vs. AES/SHA engines). | Targets cost-sensitive IoT gateways with Linux but requires external display controller and lacks native touchscreen ADC. | Choose when higher CPU clock speed is prioritized over integrated graphics and analog sensing. |
Compared with ATSAMA5D34A-CUR, ATSAMA5D31A-CUR retains EMAC and LCDC while omitting GMAC - making it optimal for cost-constrained industrial HMIs needing 100 Mbps Ethernet and rich GUIs. Against i.MX6ULL, ATSAMA5D31A-CUR delivers superior integration for display/touch/analog functions but trades peak CPU frequency for deterministic peripheral latency.
Availability
ATSAMA5D31A-CUR is available at Aetrix Electronics and suitable for industrial control panels, smart energy gateways, and battery-powered HMI terminals requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for ATSAMA5D31A-CUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full support for the SAMA5D3 series, delivering high-reliability microprocessors for industrial, automotive, and IoT applications.
The SAMA5D3 product line was designed specifically for high-integration, Linux-capable embedded systems demanding rich graphics, multiple industrial interfaces (CAN/Ethernet), and hardware-enforced security - targeting control panels, HMIs, and edge gateways.
FAQ
What is the maximum operating frequency of the ATSAMA5D31A-CUR?
The ATSAMA5D31A-CUR operates at a maximum CPU frequency of 536 MHz, as specified in the official datasheet (11121C–ATARM–15-Oct-13). This frequency is achieved using the internal PLL and is validated across temperature and voltage ranges. The ATSAMA5D31A-CUR does not support overclocking beyond this rated speed, and system stability depends on proper DDR2 timing and power delivery compliance.
Does the ATSAMA5D31A-CUR include a Gigabit Ethernet MAC?
No, the ATSAMA5D31A-CUR does not include a Gigabit Ethernet MAC (GMAC). Per Table 1-1 "SAMA5D3 Device Differences", GMAC is present in SAMA5D33/34/35/36 but explicitly omitted in SAMA5D31. Instead, ATSAMA5D31A-CUR integrates a 10/100 Mbps Ethernet MAC (EMAC), which is fully functional and IEEE 802.3 compliant.
Which packages are supported by the ATSAMA5D31A-CUR?
The ATSAMA5D31A-CUR is offered exclusively in the 324-ball LFBGA package (15 × 15 mm, 0.8 mm pitch), as confirmed in Section 4 "Package and Pinout" of the datasheet. The alternate 324-ball TFBGA (12 × 12 mm, 0.5 mm pitch) is available for other SAMA5D3 variants but not for ATSAMA5D31A-CUR.
How many CAN controllers are integrated into the ATSAMA5D31A-CUR?
The ATSAMA5D31A-CUR integrates two fully compliant CAN 2.0 Part A and Part B controllers (CAN0 and CAN1), each with eight dedicated mailboxes, message filtering, and timestamping capability. This is confirmed in both the device differences table and peripheral feature list of the ATSAMA5D31A-CUR datasheet.
What security features are implemented in hardware on the ATSAMA5D31A-CUR?
The ATSAMA5D31A-CUR implements hardware-accelerated AES-256/TDES encryption, SHA-256 hashing, True Random Number Generation (TRNG), and Atmel Secure Boot - all confirmed in the "Security" section of the datasheet. These features operate independently of the CPU core and are accessible via dedicated peripheral registers, enabling secure firmware updates and cryptographic operations without software overhead.
ATSAMA5D31A-CUR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- 324-LFBGA
- Series:
- SAMA5D3
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A5
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 536MHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- LPDDR, LPDDR2, DDR2
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- LCD, Touchscreen
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 (3)
- Voltage - I/O:
- 1.2V, 1.8V, 3.3V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- AES, SHA, TDES, TRNG
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 324-LFBGA (15x15)
- Additional Interfaces:
- I2C, MMC/SD/SDIO, SPI, SSC, UART, USART
ATSAMA5D31A-CUR FAQ
1.How can I place an order for ATSAMA5D31A-CUR through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMA5D31A-CUR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMA5D31A-CUR reliable?
The price and inventory of ATSAMA5D31A-CUR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMA5D31A-CUR is usually 5 days.
3.What payment methods are accepted for ATSAMA5D31A-CUR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMA5D31A-CUR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMA5D31A-CUR?
ATSAMA5D31A-CUR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMA5D31A-CUR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMA5D31A-CUR?
For technical support, including ATSAMA5D31A-CUR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMA5D31A-CUR requirements.
6.How does Aetrix verify that ATSAMA5D31A-CUR is sourced from the original manufacturer or authorized distributors?
All ATSAMA5D31A-CUR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMA5D31A-CUR meets industry standards.
7.What is the process for return or replacement of ATSAMA5D31A-CUR?
All ATSAMA5D31A-CUR units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMA5D31A-CUR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMA5D31A-CUR part is unused and in its original packaging.
Return procedure for ATSAMA5D31A-CUR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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