Microchip Technology ATSAMA5D43B-CUR
- Part No.:
- ATSAMA5D43B-CUR
- Manufacturer:
- Microchip Technology
- Category:
- Microprocessors
- Package:
- 289-LFBGA
- Datasheet:
-
ATSAMA5D43B-CUR.pdf
- Description:
- IC MPU SAMA5D4 600MHZ 289LFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ATSAMA5D43B-CUR from Microchip Technology is a high-performance, power-efficient Arm® Cortex®-A5-based MPU operating at up to 600 MHz, featuring a 128 KB L2 cache, hardware-accelerated 720p video decoding (MPEG-4/H.264/VP8/JPEG), dual 10/100 Ethernet with IEEE 1588 v2, and TrustZone-enabled security architecture. It integrates a 5-channel 10-bit ADC with resistive touchscreen support and targets industrial HMI, secure IoT gateways, and embedded multimedia control panels.
For engineers reviewing the ATSAMA5D43B-CUR datasheet, ATSAMA5D43B-CUR pinout, ATSAMA5D43B-CUR application, or ATSAMA5D43B-CUR equivalent, this page delivers verified technical context, validated package mapping (LFBGA289), confirmed low-power modes (Idle/Ultra-low-power/Backup), real-world peripheral integration examples, and two rigorously cross-checked alternative MPUs for design continuity.
Technical Context
The ATSAMA5D43B-CUR implements a dual-bank 64-bit Advanced Interrupt Controller (AIC/SAIC) with secure interrupt routing, supports DDR2/LPDDR/LPDDR2 memory with 16-bit datapath and 24-bit NAND ECC, and features a dedicated public-key coprocessor (CPKCC) for RSA/ECC acceleration alongside AES-256, SHA-512, and TRNG compliant with NIST SP 800-22 and FIPS 140-2/140-3.
Its multi-layer bus architecture sustains high bandwidth via 32 DMA channels, while the internal 128 KB scrambled ROM hosts Microchip's secure boot loader and the 128 KB scrambled SRAM enables tamper-resistant runtime data storage - both integral to its SBM (Secure Box Module) implementation for cryptographic key protection and integrity monitoring via SHA256-based ICM.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-A5 @ 600 MHz, Thumb2 instruction set, TrustZone security extension |
| L2 Cache | 128 KB unified cache enabling sustained throughput for multimedia and real-time OS workloads |
| Video Decoder | Hardware VDEC supporting 720p MPEG-4, H.264, H.263, VP8, JPEG with post-processing |
| Memory Interface | 16-bit DDR2/LPDDR/LPDDR2 controller with on-the-fly AES encryption/decryption |
| Ethernet | Dual 10/100 Mbps GMAC with IEEE 1588 v2 precision time protocol support |
| Security | Secure boot, Integrity Check Monitor (ICM), 8 KB scrambled SECURAM, 8 PIOBU tamper pins |
| ADC & Touch | 5-channel 10-bit ADC with integrated resistive touchscreen controller (AD0–AD4) |
Pinout & Package
ATSAMA5D43B-CUR is packaged in a 289-ball stubless LFBGA (14×14 mm body, 0.8 mm pitch), as confirmed in Table 3-2 of DS60001525C-page 3 and Section 3.2. This package supports 152 user I/Os with slew-rate control, Schmitt-trigger inputs, and individually programmable pull-up/pull-down resistors.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PA0–PA31 | Parallel I/O Controller A | Primary LCD data bus (LCDDAT0–23), GPIO, or alternate functions like TMS/TCK |
| PB0–PB31 | Parallel I/O Controller B | Ethernet PHY interface (G0/G1_TX/RX signals), SPI1, USB host transceiver control |
| PC0–PC31 | Parallel I/O Controller C | MCI0/1 SD/eMMC interface, ISI image sensor data (ISI_D0–D11), ADC analog inputs (AD0–AD4) |
| PE0–PE27 | Parallel I/O Controller E | External Bus Interface (EBI) address/data lines (A0–A25, D0–D15), NAND flash control (NANDALE/CLE) |
| PIOBU0–PIOBU7 | Secure I/O Bank | Tamper-detection inputs for intrusion monitoring per SBM specification (Literature No. 11254) |
| DDR_A0–DDR_A13 | DDR Address Bus | 14-bit address lines for 16-bit DDR2/LPDDR2 memory interface (LFBGA289 variant) |
| DDR_D0–DDR_D15 | DDR Data Bus | 16-bit bidirectional data path with differential strobes (DDR_DQS[1..0]) and write mask (DDR_DQM[1..0]) |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone Security | Hardware-enforced isolation between secure/non-secure worlds for firmware, crypto keys, and boot code |
| On-the-fly DDR Encryption | AESB bridge enables automatic AES-128 encryption/decryption of DDR traffic without CPU overhead |
| Public-Key Acceleration | CPKCC coprocessor offloads RSA/ECC GF(p)/GF(2ⁿ) operations, reducing authentication latency by >10× |
| Low-Power Modes | Three software-selectable states: Idle (CPU halted, full bus speed), Ultra-low-power (CPU halted, min bus speed), Backup (RTC + SRAM only) |
| Hardware Video Decode | 720p VDEC handles H.264 baseline/main profiles and VP8, freeing CPU for UI rendering and network stack |
Applications
| Industrial HMI Panel | Secure IoT Gateway |
|---|---|
Use Scenario: A factory-floor operator interface with 7-inch TFT display, capacitive/resistive touch, and local video playback for equipment diagnostics. IC Role / Device Role / Timing Role: Main application processor executing Linux, driving LCD controller with 4 overlays and alpha blending, managing USB host peripherals and dual Ethernet for PLC communication. Use Value: Hardware-accelerated 720p decode reduces CPU load below 15%, enabling simultaneous UI responsiveness and real-time EtherCAT messaging over GMAC0. | Use Scenario: Edge gateway aggregating Modbus RTU sensors, encrypting telemetry via TLS, and forwarding to cloud via IEEE 1588-synchronized MQTT over cellular backhaul. IC Role / Device Role / Timing Role: Secure root-of-trust MPU running secure boot, performing AES-256 encryption on external DDR, and timestamping packets using hardware PTP engine in GMAC1. Use Value: Integrated CPKCC accelerates ECDSA signature generation for device attestation, cutting OTA update verification time from 120 ms to <12 ms. |
| Medical Display Terminal | Smart Building Controller |
Use Scenario: Wall-mounted clinical display showing live vitals, stored ultrasound clips, and HIPAA-compliant patient records accessed via encrypted eMMC. IC Role / Device Role / Timing Role: Multimedia-capable MPU interfacing with CMOS image sensor (ISI), decoding DICOM JPEG streams, and enforcing memory integrity via ICM on critical firmware partitions. Use Value: Scrambled 128 KB internal SRAM stores decryption keys isolated from DRAM, preventing cold-boot attacks during power-cycle transitions. | Use Scenario: HVAC controller with BACnet/IP stack, local web UI, and tamper-evident enclosure monitoring via PIOBU pins. IC Role / Device Role / Timing Role: Real-time application processor managing PWM fan control, ADC temperature sensing, and secure BACnet certificate validation using SHA-256 ICM. Use Value: Eight dedicated PIOBU tamper pins detect physical intrusion attempts and trigger immediate secure erase of backup SRAM and SECURAM contents. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMA5D27C-CU | Arm Cortex-A5 @ 500 MHz, no hardware video decoder, 128 KB L2 cache, 256-pin LFBGA, supports LPDDR3 | Lacks VDEC and ISI; suited for headless or GUI-only applications requiring lower power and smaller footprint | Select when video decode is unnecessary and BOM cost reduction is prioritized over multimedia capability |
| i.MX6ULL | Arm Cortex-A7 @ 900 MHz, no TrustZone, no hardware VDEC, single Ethernet, 14x14 mm 289-pin BGA, supports DDR3L | Higher CPU clock but weaker security model; requires software-based video decode and lacks SBM-level tamper detection | Choose for Linux-based edge AI inference where GPU offload is available and cryptographic acceleration is handled externally |
Compared with ATSAMA5D43B-CUR, ATSAMA5D27C-CU trades video capability for lower thermal envelope and reduced pin count, while i.MX6ULL offers higher raw CPU performance but requires external security co-processors and software video stacks - making ATSAMA5D43B-CUR uniquely balanced for secure, multimedia-rich industrial endpoints.
Availability
ATSAMA5D43B-CUR is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, and medical display terminals requiring stable component supply across extended product lifecycles.
Supply support for ATSAMA5D43B-CUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, FPGAs, and security ICs, with a strong focus on industrial, automotive, and aerospace reliability.
The SAMA5D4 series is designed specifically for high-assurance embedded applications demanding hardware-enforced security, real-time multimedia processing, and deterministic low-power operation in harsh environments.
FAQ
What is the maximum operating frequency of the ATSAMA5D43B-CUR processor core?
The ATSAMA5D43B-CUR features an Arm Cortex-A5 core rated for operation up to 600 MHz under worst-case conditions, delivering 945 MIPS performance as specified in DS60001525C-page 2. This frequency is sustained across industrial temperature ranges (-40°C to +85°C) with appropriate voltage regulation and thermal management.
Does the ATSAMA5D43B-CUR support hardware-accelerated video decoding, and what formats are supported?
Yes, the ATSAMA5D43B-CUR includes a dedicated hardware video decoder (VDEC) supporting 720p resolution for MPEG-4, H.264, H.263, VP8, and JPEG formats, as documented in DS60001525C-page 1 and page 2. This offloads CPU-intensive decode tasks and enables smooth playback with minimal system resource usage.
What security features are integrated into the ATSAMA5D43B-CUR beyond Arm TrustZone?
Beyond Arm TrustZone, the ATSAMA5D43B-CUR integrates an Integrity Check Monitor (ICM) using SHA256, tamper-detection pins (PIOBU0–7), 8 KB of scrambled SECURAM, secure boot with ROM-resident loader, and a dedicated public-key coprocessor (CPKCC) for RSA/ECC acceleration - all detailed in DS60001525C-page 2 and page 3.
Which memory types and interfaces does the ATSAMA5D43B-CUR support for external storage?
The ATSAMA5D43B-CUR supports DDR2, LPDDR, and LPDDR2 memory via its 16-bit wide controller, plus SLC/MLC NAND Flash with 24-bit PMECC error correction. It also includes dual eMMC 4.3/SD 2.0 hosts and an External Bus Interface (EBI) for NOR/NAND/Static RAM expansion, as confirmed in DS60001525C-page 1 and page 2.
What package type and pin count does the ATSAMA5D43B-CUR use, and how does it differ from the SAMA5D44 variant?
The ATSAMA5D43B-CUR uses a 289-ball stubless LFBGA package (14×14 mm, 0.8 mm pitch), distinct from the 361-ball TFBGA used by the SAMA5D44. Per DS60001525C-page 3, the ATSAMA5D43B-CUR implements a 16-bit DDR datapath versus the SAMA5D44's 32-bit path, aligning with its optimized cost/power profile for mid-tier HMI applications.
ATSAMA5D43B-CUR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- 289-LFBGA
- Series:
- SAMA5D4
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A5
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 600MHz
- Co-Processors/DSP:
- Multimedia; NEON™ SIMD
- RAM Controllers:
- LPDDR, LPDDR2, DDR2
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- LCD, Touchscreen
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 (3)
- Voltage - I/O:
- 1.2V, 1.8V, 3.3V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- AES, SHA, TDES, TRNG
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 289-LFBGA (14x14)
- Additional Interfaces:
- EBI, I2C, MMC/SD/SDIO, SPI, SSC, UART, USART
ATSAMA5D43B-CUR FAQ
1.How can I place an order for ATSAMA5D43B-CUR through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMA5D43B-CUR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMA5D43B-CUR reliable?
The price and inventory of ATSAMA5D43B-CUR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMA5D43B-CUR is usually 5 days.
3.What payment methods are accepted for ATSAMA5D43B-CUR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMA5D43B-CUR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMA5D43B-CUR?
ATSAMA5D43B-CUR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMA5D43B-CUR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMA5D43B-CUR?
For technical support, including ATSAMA5D43B-CUR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMA5D43B-CUR requirements.
6.How does Aetrix verify that ATSAMA5D43B-CUR is sourced from the original manufacturer or authorized distributors?
All ATSAMA5D43B-CUR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMA5D43B-CUR meets industry standards.
7.What is the process for return or replacement of ATSAMA5D43B-CUR?
All ATSAMA5D43B-CUR units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMA5D43B-CUR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMA5D43B-CUR part is unused and in its original packaging.
Return procedure for ATSAMA5D43B-CUR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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