Microchip Technology ATSAMR34J18B-I/7JX
- Part No.:
- ATSAMR34J18B-I/7JX
- Manufacturer:
- Microchip Technology
- Category:
- RF Transceiver ICs
- Package:
- 64-TFBGA
- Datasheet:
-
ATSAMR34J18B-I/7JX.pdf
- Description:
- IC RF TXRX+MCU 802.15.4 64TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:760
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ATSAMR34J18B-I/7JX from Microchip Technology is an ultra-low-power System-in-Package (SiP) microcontroller integrating a 32-bit ARM Cortex-M0+ CPU (48 MHz), 256 KB Flash, 32 KB SRAM, 8 KB low-power SRAM, and a LoRa®/FSK UHF transceiver supporting 137–1020 MHz bands with +20 dBm max output power. It targets battery-powered remote sensor nodes and industrial LoRaWAN™ end-devices requiring USB-based firmware updates.
For engineers reviewing the ATSAMR34J18B-I/7JX datasheet, ATSAMR34J18B-I/7JX pinout, ATSAMR34J18B-I/7JX application, or ATSAMR34J18B-I/7JX equivalent, key selection considerations include integrated USB 2.0 interface (SAM R34 variant only), tri-band LoRa transceiver performance, SleepWalking peripheral wake-up capability, and 64-ball 6×6 mm TFBGA package compatibility with industrial temperature range (−40°C to +85°C).
Technical Context
The ATSAMR34J18B-I/7JX implements a tightly coupled SiP architecture where the ARM Cortex-M0+ core communicates with the LoRa transceiver via SERCOM4 (dedicated internal SPI interface), enabling deterministic packet handling without CPU intervention. Its dual PLL system (DFLL48M + FDPLL96M) supports independent clock domains for MCU, RF, and peripherals-critical for simultaneous high-speed processing and low-noise RF operation.
Power management leverages hardware-controlled domain gating, Backup/Sleep modes with retention, and SleepWalking peripherals that autonomously process ADC conversions or event-triggered DMA transfers before waking the CPU. The transceiver integrates a fully synthesized RF front-end with automatic frequency control (AFC), CAD detection, and configurable PA_BOOST/RFO_HF/RFI_HF signal routing for HF band operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0+, 48 MHz max - delivers 2.46 CoreMark®/MHz efficiency for real-time LoRa protocol stack execution |
| Memory | 256 KB Flash / 32 KB SRAM / 8 KB LP-SRAM - enables full LoRaWAN Class A/B/C stack plus application logic with battery-backed data retention |
| Transceiver Bands | 137–175 MHz, 410–525 MHz, 862–1020 MHz - supports global LoRa regional plans (EU868, US915, AS923, IN865) without external filters |
| Output Power | +20 dBm (100 mW) max at VDDANA > 2.4 V - achieves >168 dB link budget for multi-kilometer rural sensor coverage |
| RX Sensitivity | −136 dBm (LoRaWAN™ mode), −148 dBm (proprietary narrowband) - enables reliable reception under deep fading or interference |
| USB Interface | Full-speed USB 2.0 (12 Mbps), 8 endpoints - allows direct PC connection for secure firmware updates and debug without external bridge ICs |
| Package | 64-ball 6×6 mm TFBGA (7JX) - provides compact RF-optimized layout with dedicated GND_RF and VDDANA planes per datasheet land pattern |
Pinout & Package
ATSAMR34J18B-I/7JX uses a 64-ball TFBGA (7JX) package with 27 programmable I/O pins, dedicated RF supply rails (VDDANA, VR_PA, VR_ANA), and isolated ground domains (GND_RF, GNDANA). Pin functions are multiplexed across 9 peripheral options (A–I), with SERCOM4 pins (PB30/PB31/PC18/PC19) hardwired to the transceiver interface.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PA_BOOST | RF Power Amplifier Enable | Active-high control for +20 dBm HF band transmission; requires external matching network per AN3124 |
| RFO_HF | High-Frequency RF Output | Differential RF output port for 410–525 MHz and 862–1020 MHz bands; connects to balun or PA stage |
| RFI_HF | High-Frequency RF Input | Differential RF input port for HF bands; integrated LNA with −136 dBm sensitivity in LoRa mode |
| RXTX | Transmit/Receive Switch Control | Single-pin antenna switch control for T/R diversity; synchronizes PA/LNA enable timing per TRX timing diagram |
| VBAT_RF | RF Section Battery Supply | Independent 1.8–3.6 V supply for RF analog blocks; decoupling critical for phase noise and EVM compliance |
| SERCOM4 PAD[0–3] | Transceiver SPI Interface | Hardwired 4-wire SPI (MOSI/MISO/SCK/SS) between MCU and transceiver; no software configuration required |
Key Features
| Feature | Design Value |
|---|---|
| SleepWalking Peripherals | ADC, TC, and SERCOM can autonomously sample, time-stamp, and trigger DMA transfers while CPU remains in Standby mode-reducing average current to <2 μA in sensor polling cycles |
| LoRa Transceiver Integration | Tri-band RF front-end with on-die synthesizer (61 Hz resolution), AFC, and CAD engine eliminates need for external RFIC, SAW filters, or VCO tuning components |
| USB Firmware Update Path | Embedded USB device/host supports DFU class and CDC ACM - enables field upgrades over USB without JTAG debugger or external programmer |
| Hardware Security | AES-128 engine + TRNG + secure boot ROM - protects LoRa join keys and firmware integrity against physical and side-channel attacks |
| Event System | 12-channel asynchronous event router - allows peripherals (e.g., AC, ADC, RTC) to directly trigger actions (DMA, TC start, interrupt) without CPU involvement |
Applications
| Smart Agriculture Sensor Node | Industrial Asset Tracker |
|---|---|
Use Scenario: Soil moisture, temperature, and humidity monitoring in remote fields with solar/battery hybrid power. IC Role / Device Role / Timing Role: Primary SoC managing sensor acquisition, LoRaWAN MAC layer, adaptive TX power control, and USB-based configuration. Use Value: −136 dBm RX sensitivity and +20 dBm TX enable 5 km line-of-sight transmission; SleepWalking reduces average current to 8 μA during 15-minute sampling intervals. |
Use Scenario: GPS-enabled container tracking across logistics hubs with geofence alerts and tamper detection. IC Role / Device Role / Timing Role: Central controller interfacing GPS module, accelerometer, and LoRa transceiver; RTC maintains accurate timestamping for location reports. Use Value: Integrated USB allows depot technicians to reprogram firmware or update LoRa regional parameters without specialized tools; 8 KB LP-SRAM retains GPS logs during power loss. |
| Smart Utility Meter | Environmental Air Quality Monitor |
Use Scenario: Gas/water meter reading with pulse counting, pressure sensing, and battery life >10 years. IC Role / Device Role / Timing Role: Low-power host executing DLMS/COSEM over LoRaWAN; uses Backup mode to retain metering registers during main power outage. Use Value: Hardware AES encryption secures consumption data; 12-bit ADC with oversampling achieves ±0.5% accuracy on analog pressure sensors without external op-amps. |
Use Scenario: Urban PM2.5, NO₂, and CO monitoring with meshed LoRa backhaul to city gateway. IC Role / Device Role / Timing Role: Multi-sensor aggregator running proprietary FSK protocol for local mesh relay; uses Event System to synchronize ADC sampling with gas sensor preheat cycles. Use Value: Tri-band support allows seamless deployment across EU868 (868 MHz) and US915 (915 MHz) regions; −148 dBm narrowband RX extends mesh hop range in dense urban RF environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LoRa sub-GHz SoC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMR35J18B-I/7JX | No USB interface; identical MCU core, memory, RF specs, and pinout | Suitable for cost-sensitive, non-USB field deployments (e.g., sealed meters) | Select when USB programming/debug is unnecessary and BOM cost reduction is prioritized |
| STM32WL55JC | ARM Cortex-M4 core, 256 KB Flash, single-band (Sub-GHz only), no USB, different package (QFN48) | Better DSP performance for proprietary modulation; lacks tri-band flexibility and USB update path | Select when advanced signal processing (e.g., FFT-based spectrum analysis) is required and regional band coverage is fixed |
Compared with ATSAMR34J18B-I/7JX, ATSAMR35J18B-I/7JX removes USB but retains full RF and MCU compatibility for drop-in replacement in non-USB designs, while STM32WL55JC trades tri-band LoRa support and USB for higher compute throughput and lower package cost-making it suitable for fixed-frequency, compute-intensive edge analytics.
Availability
ATSAMR34J18B-I/7JX is available at Aetrix Electronics and suitable for smart agriculture sensor nodes, industrial asset trackers, utility meters, environmental monitors, and LoRaWAN gateway edge controllers requiring stable component supply across extended product lifecycles.
Supply support for ATSAMR34J18B-I/7JX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, and connectivity solutions, with a focus on robust, low-power, and secure embedded systems for industrial, automotive, and IoT markets.
ATSAMR34J18B-I/7JX belongs to Microchip's SAM R34 family of LoRa-integrated SiPs, designed specifically for ultra-low-power, long-range wireless sensor networks where regulatory compliance, battery longevity, and firmware update flexibility are critical.
FAQ
What is the maximum transmit power supported by ATSAMR34J18B-I/7JX?
ATSAMR34J18B-I/7JX supports up to +20 dBm (100 mW) output power in the HF bands (410–525 MHz and 862–1020 MHz) when VDDANA exceeds 2.4 VDC. This is achieved using the internal PA_BOOST amplifier stage, and requires proper RF matching per Microchip Application Note AN3124. Regulatory limits apply per region (e.g., +14 dBm EIRP in EU868).
Does ATSAMR34J18B-I/7JX support LoRaWAN Class B or Class C operation?
Yes, ATSAMR34J18B-I/7JX supports all LoRaWAN classes (A, B, C) through its integrated transceiver and sufficient RAM/Flash resources. The 32 KB SRAM and 256 KB Flash accommodate certified LoRaWAN stacks (e.g., Mbed OS LoRaWAN or Semtech Basic MAC), and the RTC with alarm capability enables precise Class B beacon scheduling.
How is the USB interface implemented on ATSAMR34J18B-I/7JX?
ATSAMR34J18B-I/7JX integrates a full-speed USB 2.0 peripheral with embedded device and host functionality, eight endpoints, and on-chip PHY. It supports standard USB classes including CDC ACM (virtual COM port) and DFU (device firmware upgrade), enabling direct firmware updates and debug without external USB-to-UART bridges.
Can ATSAMR34J18B-I/7JX operate in the 169 MHz band used in China?
Yes, ATSAMR34J18B-I/7JX covers 137–175 MHz, which includes the Chinese 169 MHz ISM band (169.4–169.7 MHz). Its LoRa transceiver supports channel spacing down to 61 Hz and programmable center frequencies, allowing compliant implementation of regional protocols like CLAA (China LoRa Alliance Association) with appropriate firmware configuration.
What debugging interfaces are available for ATSAMR34J18B-I/7JX?
ATSAMR34J18B-I/7JX provides two-pin Serial Wire Debug (SWD) interface (SWCLK and SWDIO) compatible with Atmel-ICE, SAM-ICE, and third-party debuggers. It supports non-intrusive on-chip debugging, flash programming, and real-time trace via the Micro Trace Buffer (MTB), with no impact on USB or RF functionality during active debug sessions.
ATSAMR34J18B-I/7JX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 64-TFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- TxRx + MCU
- RF Family/Standard:
- 802.15.4
- Protocol:
- LoRa™
- Modulation:
- FSK, GFSK, GMSK, MSK, OOK
- Frequency:
- 137MHz ~ 175MHz, 410MHz ~ 525MHz, 862MHz ~ 1.02GHz
- Data Rate (Max):
- -
- Power - Output:
- 20dBm
- Sensitivity:
- -148dBm
- Memory Size:
- 256kB Flash, 32kB SRAM
- Serial Interfaces:
- I2S, SPI, USART, USB
- GPIO:
- 27
- Voltage - Supply:
- 1.8V ~ 3.63V
- Current - Receiving:
- 14.8mA ~ 15.8mA
- Current - Transmitting:
- 32.5mA ~ 94.5mA
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 64-TFBGA (6x6)
ATSAMR34J18B-I/7JX FAQ
1.How can I place an order for ATSAMR34J18B-I/7JX through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMR34J18B-I/7JX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMR34J18B-I/7JX reliable?
The price and inventory of ATSAMR34J18B-I/7JX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMR34J18B-I/7JX is usually 5 days.
3.What payment methods are accepted for ATSAMR34J18B-I/7JX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMR34J18B-I/7JX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMR34J18B-I/7JX?
ATSAMR34J18B-I/7JX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMR34J18B-I/7JX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMR34J18B-I/7JX?
For technical support, including ATSAMR34J18B-I/7JX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMR34J18B-I/7JX requirements.
6.How does Aetrix verify that ATSAMR34J18B-I/7JX is sourced from the original manufacturer or authorized distributors?
All ATSAMR34J18B-I/7JX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMR34J18B-I/7JX meets industry standards.
7.What is the process for return or replacement of ATSAMR34J18B-I/7JX?
All ATSAMR34J18B-I/7JX units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMR34J18B-I/7JX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMR34J18B-I/7JX part is unused and in its original packaging.
Return procedure for ATSAMR34J18B-I/7JX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ATSAMR34J18B-I/7JX Tags

-
ESP32-D0WD-V3
Espressif Systems

-
ESP8266EX
Espressif Systems

-
ESP32-S3
Espressif Systems

-
NRF24L01P-R7
Nordic Semiconductor ASA

-
NRF24L01P-R
Nordic Semiconductor ASA

-
ESP32-U4WDH
Espressif Systems

-
DA14531-00000OG2
Renesas

-
ESP32-C6FH4
Espressif Systems

-
DA14531-00000FX2
Renesas

-
NRF24L01P-T
Nordic Semiconductor ASA

-
NRF52810-QCAA-R
Nordic Semiconductor ASA

-
ESP32-S3FN8
Espressif Systems
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

