Microchip Technology ATSAMR35J16B-I/7JX
- Part No.:
- ATSAMR35J16B-I/7JX
- Manufacturer:
- Microchip Technology
- Category:
- RF Transceiver ICs
- Package:
- 64-TFBGA
- Datasheet:
-
ATSAMR35J16B-I/7JX.pdf
- Description:
- IC RF TXRX+MCU 802.15.4 64TFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ATSAMR35J16B-I/7JX from Microchip Technology is an ultra-low-power System-in-Package (SiP) microcontroller integrating a 32-bit ARM Cortex-M0+ CPU (48 MHz), 64 KB Flash, 8 KB SRAM, 4 KB low-power SRAM, and a LoRa®/FSK UHF transceiver covering 137–1020 MHz with +20 dBm max output power. It operates from 1.8–3.6 V and targets battery-powered remote sensor nodes in industrial IoT and smart utility metering.
For engineers reviewing the ATSAMR35J16B-I/7JX datasheet, ATSAMR35J16B-I/7JX pinout, ATSAMR35J16B-I/7JX application, or ATSAMR35J16B-I/7JX equivalent, key selection considerations include its LoRaWAN™-compliant -136 dBm RX sensitivity, 27 GPIOs in 6×6 mm TFBGA, SleepWalking peripheral wake-up capability, and absence of USB interface (distinguishing it from SAM R34 variants).
Technical Context
The ATSAMR35J16B-I/7JX implements a dual-domain clock architecture with DFLL48M and FDPLL96M for dynamic frequency scaling, enabling independent peripheral clock gating to minimize active and standby power. Its transceiver integrates tri-band RF front-end (HF/LF paths), fractional-N PLL synthesizer (61 Hz resolution), and hardware-accelerated LoRa packet engine with CRC and automatic frequency control.
On-chip peripherals include three 16-bit Timer/Counters (TC), three Timer/Counters for Control (TCC) supporting PWM generation with dead-time insertion, a 12-bit 1 Msps ADC with hardware oversampling up to 16-bit, two analog comparators, and a 12-channel event system allowing asynchronous peripheral interaction in Standby mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0+ at 48 MHz (2.46 CoreMark/MHz); enables real-time LoRa MAC layer execution with minimal latency. |
| Memory | 64 KB Flash / 8 KB SRAM / 4 KB LP-SRAM; sufficient for compact LoRaWAN Class A end-node firmware with retained state during deep sleep. |
| Transceiver Bands | 137–175 MHz, 410–525 MHz, 862–1020 MHz; supports global sub-GHz ISM bands without external band-switching components. |
| Max TX Power | +20 dBm (100 mW) at VDDANA > 2.4 V; meets ETSI EN 300 220 and FCC Part 15.247 regulatory limits for long-range node transmission. |
| RX Sensitivity | -136 dBm (LoRaWAN™ modes); achieves >15 km outdoor range at SF12/125 kHz in rural deployments. |
| Low-Power Modes | Standby mode draws <1.5 µA with RTC and 8 KB LP-SRAM retained; enables 10+ year battery life in periodic sensor reporting. |
| Supply Voltage | 1.8–3.6 V operation; compatible with single-cell Li-SOCl₂ (3.6 V) or two-cell alkaline (3.0 V) primary batteries. |
Pinout & Package
ATSAMR35J16B-I/7JX is housed in a 64-ball 6×6 mm Thin Fine-Pitch Ball Grid Array (TFBGA) package (7JX), with 27 programmable I/O pins, dedicated RF input/output terminals (RFI_HF/RFO_HF/RFI_LF/RFO_LF), and separate analog/digital power domains (VDDANA/VDDIO/VDDCORE/VSW).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RFI_HF | High-frequency RF input | Connects to external HF antenna matching network (137–175 MHz or 410–525 MHz bands); requires 50 Ω impedance trace. |
| RFO_HF | High-frequency RF output | Drives HF antenna via integrated PA_BOOST path; supports +20 dBm output with external filtering. |
| PA_BOOST | Power amplifier enable | Active-high control for high-efficiency 20 dBm transmit path; must be synchronized with TX timing in firmware. |
| SERCOM4/PB30–PB31 | Transceiver SPI interface | Dedicated hardware SPI bus (MOSI/MISO/SCK) internally routed to LoRa transceiver; no software bit-banging required. |
| XTA/XTB | RF oscillator crystal connections | Supports 16 MHz crystal for precise RF frequency synthesis; critical for LoRa channel accuracy and AFC stability. |
Key Features
| Feature | Design Value |
|---|---|
| LoRaWAN™-compliant transceiver | Integrated packet engine with automatic CAD, preamble detection, and CRC handles full LoRa MAC layer offload. |
| SleepWalking peripherals | ADC, TC, or SERCOM can autonomously sample, time, or receive data in Standby mode and wake CPU only on threshold/event. |
| Tri-band RF front-end | Single SiP supports global sub-GHz deployment without hardware redesign-reduces BOM and certification effort across regions. |
| Hardware-accelerated crypto | AES-128 engine and TRNG enable secure over-the-air updates and end-to-end encryption without CPU overhead. |
| Event-driven architecture | 12-channel event system allows peripherals (e.g., ADC → TC → DMA) to chain operations without CPU intervention. |
Applications
| Smart Utility Metering | Industrial Predictive Maintenance |
|---|---|
|
Use Scenario: Battery-powered gas/water meters transmitting hourly consumption data over 5–10 km to gateway. IC Role / Device Role / Timing Role: LoRa transceiver handles physical layer modulation/demodulation; Cortex-M0+ executes LoRaWAN stack and sensor polling logic. Use Value: -136 dBm sensitivity and +20 dBm output enable reliable link budget >160 dB, eliminating repeaters in dense urban deployments. |
Use Scenario: Vibration and temperature sensors on rotating machinery sending alerts when thresholds exceed predictive models. IC Role / Device Role / Timing Role: ADC oversamples accelerometer data; SleepWalking TC triggers DMA transfer to SRAM; LoRa transmits compressed FFT features. Use Value: 1.5 µA Standby current with RTC wake-up extends 2xAA battery life beyond 7 years, reducing maintenance cycles. |
| Agricultural Soil Monitoring | Asset Tracking in Logistics |
|
Use Scenario: Solar-charged soil moisture/temperature nodes deployed across 100+ hectare farms reporting daily via LoRaWAN. IC Role / Device Role / Timing Role: LP-SRAM retains calibration data during night-time sleep; SERCOM4 SPI configures transceiver for adaptive data rate (ADR). Use Value: Tri-band support allows same PCB design for EU (868 MHz), US (915 MHz), and AU (920 MHz) deployments-no regional SKUs. |
Use Scenario: Container-mounted trackers reporting GPS location every 6 hours using geofence-triggered burst transmission. IC Role / Device Role / Timing Role: External GPS module connects via SERCOM USART; TCC generates precise 6-hour intervals; LoRa sends encrypted payload. Use Value: Hardware CRC and AES-128 prevent payload tampering; 27 GPIOs support optional digital inputs for door-open detection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LoRa sub-GHz SoC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32WL55JC | ARM Cortex-M4 core (48 MHz), 256 KB Flash, dual-core LoRa + GFSK, integrated SMPS, 48-pin QFN. | Higher compute headroom for edge ML inference; lacks LP-SRAM retention and SleepWalking; smaller footprint but lower RX sensitivity (-148 dBm LoRa). | Select STM32WL55JC when requiring M4 DSP instructions or integrated DC-DC; avoid if multi-year battery life with frequent wake-ups is mandatory. |
| AX5043-1-TQ48 | Standalone LoRa transceiver IC (no MCU), 137–1050 MHz, -142 dBm sensitivity, 20 dBm output, 48-pin TQFP. | Requires external MCU (e.g., ATSAMR30G18); adds BOM cost and layout complexity but offers maximum RF performance tuning flexibility. | Select AX5043-1-TQ48 when RF coexistence in noisy environments demands discrete filter design or when existing MCU platform must be reused. |
Compared with STM32WL55JC and AX5043-1-TQ48, ATSAMR35J16B-I/7JX uniquely balances ultra-low standby current (<1.5 µA), integrated SleepWalking peripherals, and LoRaWAN-compliant RF performance in a single SiP-making it optimal for cost-sensitive, long-life sensor nodes where MCU and RF co-design reduces system-level power and size.
Availability
ATSAMR35J16B-I/7JX is available at Aetrix Electronics and suitable for smart utility metering, industrial predictive maintenance, agricultural monitoring, asset tracking, and environmental sensing requiring stable component supply across multi-year production cycles.
Supply support for ATSAMR35J16B-I/7JX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a leading provider of microcontrollers, analog, FPGA, and connectivity solutions, with a focus on reliability, security, and low-power innovation for industrial and IoT markets.
The SAM R35 product line was designed specifically for battery-operated LoRaWAN end-nodes, integrating RF, MCU, and power management into a single SiP to eliminate RF design risk and accelerate time-to-certification.
FAQ
What is the maximum transmit power supported by ATSAMR35J16B-I/7JX?
ATSAMR35J16B-I/7JX supports up to +20 dBm (100 mW) output power in the HF band when VDDANA exceeds 2.4 VDC. This is achieved using the internal PA_BOOST path and complies with ETSI EN 300 220 and FCC Part 15.247 regulations. Lower power modes (+17 dBm regulated, +13 dBm high-efficiency) are also available for optimized battery life.
Does ATSAMR35J16B-I/7JX include a USB interface?
No, ATSAMR35J16B-I/7JX does not include a USB interface. Unlike the SAM R34 family, the R35 variant omits the USB 2.0 peripheral to reduce power consumption and silicon area. Communication with the host is handled exclusively via SERCOM interfaces (e.g., USART, SPI, I²C), with SERCOM4 hardwired to the LoRa transceiver.
How many GPIO pins are available on ATSAMR35J16B-I/7JX?
ATSAMR35J16B-I/7JX provides 27 programmable general-purpose I/O pins. These are distributed across PORTA and PORTB, with multiplexing support for up to nine peripheral functions per pin (A–I). Dedicated RF pins (e.g., RFI_HF, RFO_HF) and power/ground balls are excluded from this count.
What sleep modes are supported by ATSAMR35J16B-I/7JX and what is the lowest current draw?
ATSAMR35J16B-I/7JX supports four software-selectable sleep modes: Idle, Standby, Backup, and Off. In Standby mode-with RTC and 4 KB LP-SRAM retained-the device draws less than 1.5 µA. This enables decade-long battery life in applications with infrequent wake-ups (e.g., hourly sensor reads).
Is ATSAMR35J16B-I/7JX pin-compatible with other SAM R35 variants?
Yes, all SAM R35 variants-including ATSAMR35J16B-I/7JX, ATSAMR35J17B-I/7JX, and ATSAMR35J18B-I/7JX-share identical 64-ball TFBGA (7JX) packaging and pinout. Memory differences (64 KB/128 KB/256 KB Flash) are implemented internally and do not affect board layout or signal routing.
ATSAMR35J16B-I/7JX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 64-TFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- TxRx + MCU
- RF Family/Standard:
- 802.15.4
- Protocol:
- LoRa™
- Modulation:
- FSK, GFSK, GMSK, MSK, OOK
- Frequency:
- 137MHz ~ 175MHz, 410MHz ~ 525MHz, 862MHz ~ 1.02GHz
- Data Rate (Max):
- -
- Power - Output:
- 20dBm
- Sensitivity:
- -148dBm
- Memory Size:
- 64kB Flash, 8kB SRAM
- Serial Interfaces:
- I2S, SPI, USART, USB
- GPIO:
- 27
- Voltage - Supply:
- 1.8V ~ 3.63V
- Current - Receiving:
- 14.8mA ~ 15.8mA
- Current - Transmitting:
- 32.5mA ~ 94.5mA
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 64-TFBGA (6x6)
ATSAMR35J16B-I/7JX FAQ
1.How can I place an order for ATSAMR35J16B-I/7JX through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMR35J16B-I/7JX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMR35J16B-I/7JX reliable?
The price and inventory of ATSAMR35J16B-I/7JX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMR35J16B-I/7JX is usually 5 days.
3.What payment methods are accepted for ATSAMR35J16B-I/7JX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMR35J16B-I/7JX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMR35J16B-I/7JX?
ATSAMR35J16B-I/7JX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMR35J16B-I/7JX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMR35J16B-I/7JX?
For technical support, including ATSAMR35J16B-I/7JX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMR35J16B-I/7JX requirements.
6.How does Aetrix verify that ATSAMR35J16B-I/7JX is sourced from the original manufacturer or authorized distributors?
All ATSAMR35J16B-I/7JX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMR35J16B-I/7JX meets industry standards.
7.What is the process for return or replacement of ATSAMR35J16B-I/7JX?
All ATSAMR35J16B-I/7JX units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMR35J16B-I/7JX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMR35J16B-I/7JX part is unused and in its original packaging.
Return procedure for ATSAMR35J16B-I/7JX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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