Microchip Technology ATSAMR35J17B-I/7JX
- Part No.:
- ATSAMR35J17B-I/7JX
- Manufacturer:
- Microchip Technology
- Category:
- RF Transceiver ICs
- Package:
- 64-TFBGA
- Datasheet:
-
ATSAMR35J17B-I/7JX.pdf
- Description:
- IC RF TXRX+MCU 802.15.4 64TFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ATSAMR35J17B-I/7JX from Microchip Technology is an ultra-low-power System-in-Package (SiP) microcontroller integrating a 32-bit ARM Cortex-M0+ CPU (48 MHz), 128 KB Flash, 16 KB SRAM, 8 KB low-power SRAM, and a LoRa®/FSK UHF transceiver supporting 137–1020 MHz bands with +20 dBm max output power. It targets battery-powered LPWAN sensor nodes and industrial telemetry gateways requiring long-range, sub-GHz wireless connectivity.
For engineers reviewing the ATSAMR35J17B-I/7JX datasheet, ATSAMR35J17B-I/7JX pinout, ATSAMR35J17B-I/7JX application, or ATSAMR35J17B-I/7JX equivalent, key selection criteria include LoRa modulation support, tri-band RF coverage, SleepWalking peripheral wake-up capability, 27 GPIOs in 6×6 mm TFBGA, and absence of USB interface compared to SAM R34 variants.
Technical Context
The ATSAMR35J17B-I/7JX implements a dual-domain architecture: the MCU subsystem features a 48 MHz Cortex-M0+ core with DFLL48M and FDPLL96M clock generators, while the RF subsystem integrates a fully synthesized LoRa/FSK transceiver with independent HF/LF RF paths, RFO_HF/PA_BOOST outputs, and RFI_HF/RFI_LF inputs. SERCOM4 is hardwired to the transceiver for SPI-based host control.
Power management includes four software-selectable sleep modes (Idle, Standby, Backup, Off), hardware-controlled domain gating, and SleepWalking-enabling peripherals like ADC or TC to autonomously trigger DMA or CPU wake-up without full system activation. The transceiver achieves −136 dBm LoRaWAN™ sensitivity and 168 dB link budget.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0+, 48 MHz - delivers 2.46 CoreMark/MHz for deterministic real-time LoRa packet processing. |
| Memory | 128 KB Flash / 16 KB SRAM / 8 KB LP-SRAM - supports over-the-air firmware updates and retention during deep sleep. |
| RF Bands | 137–175 MHz, 410–525 MHz, 862–1020 MHz - enables global deployment across EU868, US915, CN470, and AU915 regional LoRa plans. |
| Max TX Power | +20 dBm (100 mW) - sufficient for 10+ km outdoor range in rural LPWAN deployments without external PA. |
| Sensitivity | −136 dBm (LoRaWAN™) - ensures reliable reception at ultra-low signal levels typical of battery-operated end-nodes. |
| GPIO Count | 27 programmable I/O pins - provides ample interface flexibility for sensors, actuators, and external memory while maintaining compact SiP footprint. |
| Package | 64-ball 6×6 mm TFBGA (7JX) - enables high-density PCB layout for space-constrained IoT edge devices. |
Pinout & Package
ATSAMR35J17B-I/7JX uses a 64-ball 6×6 mm TFBGA package (7JX land pattern). Pin functions are multiplexed across 27 GPIOs and dedicated RF/analog/power terminals. Critical RF signals include RFO_HF, PA_BOOST, RFI_HF, RXTX, and VR_PA; MCU interfaces include SWDIO/SWCLK debug, SERCOMx for UART/I²C/SPI, and TC/TCC for timing-critical waveform generation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RFO_HF | High-frequency RF output | Primary antenna connection path for 410–1020 MHz band; requires matching network per frequency plan. |
| PA_BOOST | High-power amplifier enable | Controls +20 dBm output mode; must be driven high only when VDDANA > 2.4 VDC to meet spec. |
| RFI_HF | High-frequency RF input | Receives signals in 410–1020 MHz band; connected to internal LNA and demodulator chain. |
| RXTX | Transmit/receive switch control | Configures internal RF switch between TX and RX paths; critical for half-duplex LoRa operation. |
| SWDIO/SWCLK | Serial Wire Debug interface | Enables non-intrusive programming and real-time debugging without halting RF operation. |
| SERCOM4 | Transceiver host interface | Hardwired SPI bus (PB30/PB31/PC18/PC19) for register access, packet FIFO control, and CAD/RSSI readback. |
Key Features
| Feature | Design Value |
|---|---|
| Tri-band LoRa/FSK transceiver | Single SiP covers all major sub-GHz ISM bands - eliminates need for multiple SKUs or external RF front-end switching. |
| SleepWalking peripheral engine | Allows ADC, TC, or SERCOM to autonomously sample, time, or receive data and wake CPU only on threshold/event - reduces average current to µA range. |
| Hardware-accelerated LoRa packet engine | On-chip CRC, preamble detection, automatic frequency control (AFC), and CAD reduce host MCU overhead and latency for rapid channel sensing. |
| Integrated 12-bit 1 Msps ADC | Supports oversampling up to 16-bit resolution - enables direct analog sensor interfacing (e.g., temperature, humidity) without external ADC. |
| Dual-clock domain architecture | DFLL48M (digital) and FDPLL96M (fractional PLL) allow independent peripheral clock scaling - optimizes power vs. performance trade-off per subsystem. |
Applications
| Smart Agriculture Sensor Node | Industrial Asset Monitor |
|---|---|
Use Scenario: Soil moisture, temperature, and ambient light monitoring in remote fields using solar-charged batteries. IC Role / Device Role / Timing Role: ATSAMR35J17B-I/7JX acts as the primary SoC - executing LoRaWAN stack, managing sensor polling intervals via RTC alarms, and transmitting encrypted packets every 15 minutes. Use Value: −136 dBm sensitivity and 168 dB link budget ensure reliable uplink from buried or shielded enclosures; 8 KB LP-SRAM retains calibration data during multi-day sleep cycles. | Use Scenario: Vibration, temperature, and pressure logging on rotating machinery in factory environments. IC Role / Device Role / Timing Role: ATSAMR35J17B-I/7JX serves as edge intelligence node - triggering ADC sampling on accelerometer interrupt, applying FIR filtering in SRAM, and sending compressed telemetry via adaptive LoRa SF7–SF12. Use Value: SleepWalking enables continuous accelerometer monitoring at <10 µA while waking CPU only on anomaly detection - extending 2xAA battery life beyond 5 years. |
| Smart Metering Gateway | Environmental Air Quality Station |
Use Scenario: Aggregating gas/water meter readings from 50+ endpoints via private LoRa network in urban utility infrastructure. IC Role / Device Role / Timing Role: ATSAMR35J17B-I/7JX operates as Class B/C gateway controller - managing downlink scheduling, channel hopping, and AES-128 encryption/decryption for secure command delivery. Use Value: 27 GPIOs support RS-485 backhaul to central SCADA; SERCOM4's dedicated SPI interface ensures deterministic transceiver register access during concurrent packet reception. | Use Scenario: Outdoor PM2.5, NO₂, and CO monitoring with GPS-assisted geotagging in municipal air quality networks. IC Role / Device Role / Timing Role: ATSAMR35J17B-I/7JX functions as integrated sensor fusion hub - synchronizing ADC, analog comparators, and PTC touch inputs to detect particulate filter clogging or sensor drift. Use Value: On-chip TRNG and AES engine enable secure OTA firmware updates; −40°C to +85°C rating guarantees operation in unheated street cabinets. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LoRa SiP applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMR35J18B-I/7JX | 256 KB Flash / 32 KB SRAM (vs. 128 KB / 16 KB); identical RF specs and pinout | Better suited for complex LoRaWAN stacks with local data buffering or multi-region firmware images | Select when firmware size exceeds 128 KB or future-proofing for feature expansion is required. |
| STM32WL55JC | ARM Cortex-M4 core, 256 KB Flash, 64 KB SRAM, single-band (433/868/915 MHz), +16 dBm TX | Lacks tri-band coverage and SleepWalking; offers higher CPU performance but higher active current | Prefer for compute-intensive edge AI inference where LoRa bandwidth suffices and regional band lock is acceptable. |
Compared with ATSAMR35J17B-I/7JX, the J18B variant offers double memory for larger protocol stacks without changing PCB layout, while STM32WL55JC trades tri-band flexibility and ultra-low sleep current for higher processing throughput and integrated crypto acceleration - making it suitable for different architectural priorities.
Availability
ATSAMR35J17B-I/7JX is available at Aetrix Electronics and suitable for smart agriculture sensor nodes, industrial asset monitors, smart metering gateways, and environmental air quality stations requiring stable component supply across multi-year production cycles.
Supply support for ATSAMR35J17B-I/7JX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and security solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The SAM R35 product line was designed specifically for ultra-low-power, long-range LPWAN endpoints - integrating LoRa transceivers and ARM Cortex-M0+ cores into compact SiPs to eliminate RF design complexity and accelerate time-to-market for battery-operated IoT devices.
FAQ
What is the maximum transmit power supported by the ATSAMR35J17B-I/7JX?
The ATSAMR35J17B-I/7JX supports up to +20 dBm (100 mW) output power in the HF band when VDDANA exceeds 2.4 VDC. This is achieved using the PA_BOOST path and requires proper RF matching per regional frequency plan. Regulated PA mode delivers +17 dBm, and high-efficiency PA mode delivers +13 dBm - allowing optimization for range, battery life, or regulatory compliance.
Does the ATSAMR35J17B-I/7JX include a USB interface?
No, the ATSAMR35J17B-I/7JX does not include a USB interface. It belongs to the SAM R35 family, which omits the USB 2.0 peripheral present in the SAM R34 series. Communication with the ATSAMR35J17B-I/7JX is handled via SERCOM interfaces (UART/I²C/SPI), SWD debug, or the dedicated SERCOM4 SPI link to the integrated LoRa transceiver.
How many GPIO pins are available on the ATSAMR35J17B-I/7JX?
The ATSAMR35J17B-I/7JX provides 27 programmable general-purpose I/O pins. These are distributed across PORTA and PORTB, with multiplexing support for SERCOM, TC/TCC, ADC, AC, PTC, and CCL functions. All 27 pins are accessible in the 64-ball 6×6 mm TFBGA (7JX) package and retain functionality in Standby and Backup sleep modes.
What LoRa frequency bands does the ATSAMR35J17B-I/7JX support?
The ATSAMR35J17B-I/7JX supports three discrete UHF bands: 137–175 MHz, 410–525 MHz, and 862–1020 MHz. This tri-band coverage enables compliance with regional LoRaWAN specifications including EU868, US915, IN865, AU915, and KR920 without hardware modification - a key differentiator from single-band alternatives like the STM32WL55JC.
Is the ATSAMR35J17B-I/7JX qualified for industrial temperature operation?
Yes, the ATSAMR35J17B-I/7JX is rated for industrial temperature operation from −40°C to +85°C. This specification is guaranteed across all electrical characteristics, including RF performance (sensitivity, output power), MCU timing (48 MHz operation), and memory retention - making it suitable for deployment in uncontrolled environments such as outdoor utility meters, agricultural sensors, and factory-floor monitoring systems.
ATSAMR35J17B-I/7JX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 64-TFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- TxRx + MCU
- RF Family/Standard:
- 802.15.4
- Protocol:
- LoRa™
- Modulation:
- FSK, GFSK, GMSK, MSK, OOK
- Frequency:
- 137MHz ~ 175MHz, 410MHz ~ 525MHz, 862MHz ~ 1.02GHz
- Data Rate (Max):
- -
- Power - Output:
- 20dBm
- Sensitivity:
- -148dBm
- Memory Size:
- 128kB Flash, 16kB SRAM
- Serial Interfaces:
- I2S, SPI, USART, USB
- GPIO:
- 27
- Voltage - Supply:
- 1.8V ~ 3.63V
- Current - Receiving:
- 14.8mA ~ 15.8mA
- Current - Transmitting:
- 32.5mA ~ 94.5mA
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 64-TFBGA (6x6)
ATSAMR35J17B-I/7JX FAQ
1.How can I place an order for ATSAMR35J17B-I/7JX through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMR35J17B-I/7JX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMR35J17B-I/7JX reliable?
The price and inventory of ATSAMR35J17B-I/7JX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMR35J17B-I/7JX is usually 5 days.
3.What payment methods are accepted for ATSAMR35J17B-I/7JX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMR35J17B-I/7JX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMR35J17B-I/7JX?
ATSAMR35J17B-I/7JX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMR35J17B-I/7JX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMR35J17B-I/7JX?
For technical support, including ATSAMR35J17B-I/7JX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMR35J17B-I/7JX requirements.
6.How does Aetrix verify that ATSAMR35J17B-I/7JX is sourced from the original manufacturer or authorized distributors?
All ATSAMR35J17B-I/7JX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMR35J17B-I/7JX meets industry standards.
7.What is the process for return or replacement of ATSAMR35J17B-I/7JX?
All ATSAMR35J17B-I/7JX units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMR35J17B-I/7JX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMR35J17B-I/7JX part is unused and in its original packaging.
Return procedure for ATSAMR35J17B-I/7JX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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