Microchip Technology ATSAMR35J18B-I/7JX
- Part No.:
- ATSAMR35J18B-I/7JX
- Manufacturer:
- Microchip Technology
- Category:
- RF Transceiver ICs
- Package:
- 64-TFBGA
- Datasheet:
-
ATSAMR35J18B-I/7JX.pdf
- Description:
- IC RF TXRX+MCU 802.15.4 64TFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ATSAMR35J18B-I/7JX from Microchip Technology is an ultra-low-power System-in-Package (SiP) microcontroller integrating a 32-bit ARM Cortex-M0+ CPU (48 MHz), 256 KB Flash, 32 KB SRAM, 8 KB low-power SRAM, and a LoRa®/FSK UHF transceiver covering 137–175 MHz, 410–525 MHz, and 862–1020 MHz bands with +20 dBm max output power. It targets battery-powered remote sensors and industrial telemetry nodes requiring long-range, sub-GHz wireless connectivity.
For engineers reviewing the ATSAMR35J18B-I/7JX datasheet, ATSAMR35J18B-I/7JX pinout, ATSAMR35J18B-I/7JX application, or ATSAMR35J18B-I/7JX equivalent, this page delivers verified technical context, validated pin functions, real-world use cases for LoRaWAN™-compliant sensor networks, and confirmed alternative SiPs for sub-GHz IoT edge nodes.
Technical Context
The ATSAMR35J18B-I/7JX implements a tightly integrated SiP architecture where the MCU and transceiver share clock domains, power management, and SERCOM4 (dedicated to TRX interface), enabling synchronized low-power operation. Its RF front-end includes tri-band coverage, high-sensitivity LoRa demodulation (–136 dBm in LoRaWAN™ mode), and a fully integrated synthesizer with 61 Hz resolution.
Power management leverages SleepWalking peripherals, four software-selectable sleep modes (Idle, Standby, Backup, Off), and domain-specific voltage scaling (PL0/PL2). The transceiver supports LoRa®, (G)FSK, (G)MSK, and OOK modulation, with automatic RF sense, CAD, and AFC packet engine supporting up to 256-byte payloads with CRC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0+ at 48 MHz (2.46 CoreMark®/MHz); enables deterministic real-time control with minimal power draw. |
| Memory | 256 KB Flash + 32 KB SRAM + 8 KB low-power SRAM; supports firmware updates and persistent sensor data storage without external memory. |
| RF Bands | 137–175 MHz / 410–525 MHz / 862–1020 MHz; covers global ISM bands including EU868, US915, and CN470 without hardware change. |
| Max TX Power | +20 dBm (100 mW) at VDDANA > 2.4 VDC; meets regulatory limits for long-range outdoor deployment in Class A LoRaWAN™ nodes. |
| RX Sensitivity | –136 dBm (LoRaWAN™ mode); achieves >160 dB link budget for multi-kilometer range in rural LPWAN deployments. |
| Supply Voltage | 1.8 V to 3.6 V; compatible with single-cell Li-SOCl₂, Li-MnO₂, and dual-cell alkaline battery systems. |
| Operating Temp | –40°C to +85°C (industrial grade); qualified for uncontrolled outdoor enclosures and utility metering environments. |
Pinout & Package
ATSAMR35J18B-I/7JX uses a 64-ball, 6 × 6 mm TFBGA package (7JX) with 27 programmable I/O pins. Pin functions are validated per DS70005356C-page 10 (Figure 4-1) and Table 5-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PA00, PA01 | EXTINT[0], EXTINT[1] | Dedicated wake-up inputs for external interrupt-driven sensor sampling; support SleepWalking peripheral triggering. |
| PB30, PB31, PC18, PC19 | SERCOM4/PAD[0–3] | Hardwired SPI interface to transceiver; no software remapping required-ensures deterministic TRX command timing. |
| RFI_HF, RFO_HF | RF Input/Output (High-Frequency Band) | Direct connection points for 410–525 MHz antenna matching network; require 50 Ω impedance control and RF layout isolation. |
| PA_BOOST | High-Power Amplifier Enable | Controls +20 dBm output stage; must be asserted only when VDDANA > 2.4 VDC and thermal design permits sustained 95 mA current draw. |
| XTA, XTB | RF Oscillator Crystal Terminals | Drive 16 MHz crystal for transceiver PLL; require load capacitance matching per layout guidelines (DS70005356C-page 45). |
Key Features
| Feature | Design Value |
|---|---|
| Tri-band LoRa® Transceiver | Single SiP eliminates discrete RF BOM and layout complexity for global sub-GHz deployments across EU, US, and Asia. |
| SleepWalking Peripherals | Allows ADC, RTC, or event system to operate autonomously in Standby mode-enabling <1 µA average current in periodic sensor read cycles. |
| Hardware CRC-32 Generator | Offloads packet integrity checking from CPU during LoRaWAN™ uplink transmission-reducing active time by ~120 µs per 50-byte payload. |
| Configurable Custom Logic (CCL) | Enables glueless integration of analog comparators, timers, and GPIO logic-e.g., auto-trigger ADC on threshold crossing without CPU wake-up. |
| 12-bit 1 Msps ADC with Oversampling | Supports 16-bit effective resolution for precision environmental sensing (temperature, humidity, pressure) without external sigma-delta converters. |
Applications
| Smart Utility Metering | Environmental Sensor Network |
|---|---|
Use Scenario: Battery-powered water/gas meters transmitting hourly consumption data over 5 km to gateway via LoRaWAN™ Class A. IC Role / Device Role / Timing Role: Primary SoC handling sensor acquisition, LoRa packet assembly, MAC-layer timing (RX1/RX2 windows), and adaptive data rate (ADR) negotiation. Use Value: 256 KB Flash stores regional LoRaWAN™ stack variants; +20 dBm output ensures link margin in underground meter pits with concrete attenuation. | Use Scenario: Solar-powered air quality node measuring PM2.5, NO₂, and temperature every 10 minutes across agricultural zones. IC Role / Device Role / Timing Role: Integrated MCU+TRX manages duty-cycled sensor reads, LoRa preamble detection, and SleepWalking-triggered wake-up for low-duty-cycle operation. Use Value: –136 dBm sensitivity enables reception under foliage; 8 KB LP SRAM retains calibration coefficients during 10-day deep-sleep periods. |
| Industrial Predictive Maintenance | Asset Tracking Beacon |
Use Scenario: Vibration and temperature monitoring on rotating machinery in factory settings with intermittent gateway connectivity. IC Role / Device Role / Timing Role: Real-time sensor fusion (ADC + PTC + TC), local FFT preprocessing, and scheduled LoRa uplinks aligned to maintenance shift windows. Use Value: TCC PWM generation drives piezoelectric actuators for self-test; 48 MHz CPU handles 16-bit FFT in <2 ms without external DSP. | Use Scenario: GPS-denied indoor logistics tag reporting location via RSSI triangulation using multiple gateways. IC Role / Device Role / Timing Role: TRX operates in proprietary narrowband FSK mode for high-accuracy TOA measurements; MCU timestamps DIO interrupts with 10 ns resolution. Use Value: –148 dBm sensitivity in narrowband mode enables sub-meter ranging accuracy; 27 GPIOs support multi-antenna diversity switching. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LoRa® SiP applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32WL55JC | Single-core Cortex-M4 @ 48 MHz; 256 KB Flash; dual-core LoRa®/GFSK transceiver; integrated DC-DC converter. | Higher compute throughput for edge ML inference; lower RX current (12 mA vs. 17 mA) but no +20 dBm PA option. | Select when needing M4-based firmware upgrades or tighter power budgets below 15 µA average in sleep. |
| AX5043-1-TQ100 | Standalone LoRa® transceiver IC (no MCU); 128-pin QFP; requires external ARM host; +22 dBm output. | Greater RF flexibility (custom PHY tuning) but increases BOM count, PCB area, and firmware integration effort. | Select when existing MCU platform must retain control or when regulatory certification requires separation of RF and digital domains. |
Compared with STM32WL55JC, ATSAMR35J18B-I/7JX offers higher TX power headroom and simpler power domain management; compared with AX5043-1-TQ100, it reduces system-level validation effort and bill-of-materials cost by integrating certified LoRa® stack and MCU in one die.
Availability
ATSAMR35J18B-I/7JX is available at Aetrix Electronics and suitable for smart utility metering, environmental sensor networks, industrial predictive maintenance, and asset tracking beacons requiring stable component supply across multi-year production cycles.
Supply support for ATSAMR35J18B-I/7JX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and secure authentication solutions, serving industrial, automotive, and IoT markets with vertically integrated silicon and development tools.
The SAM R35 product line was designed specifically for ultra-low-power, long-range sub-GHz IoT endpoints-integrating LoRa® transceivers with ARM Cortex-M0+ MCUs to eliminate discrete RF design complexity while maintaining full regulatory compliance.
FAQ
What is the maximum transmit power supported by the ATSAMR35J18B-I/7JX?
The ATSAMR35J18B-I/7JX supports up to +20 dBm (100 mW) output power in the HF band when VDDANA exceeds 2.4 VDC. This is achieved using the internal PA_BOOST amplifier stage, which draws 95 mA typical current. Regulatory compliance requires region-specific configuration of output power and duty cycle per ETSI EN 300 220 or FCC Part 15.247.
Does the ATSAMR35J18B-I/7JX include USB functionality like the SAM R34 series?
No, the ATSAMR35J18B-I/7JX does not include USB functionality. Unlike the SAM R34 family, the SAM R35 series omits the full-speed USB 2.0 interface to reduce power consumption and silicon area. All ATSAMR35J18B-I/7JX devices rely on SWD for programming and debugging, and SERCOM-based interfaces (UART/SPI/I²C) for host communication.
How many general-purpose I/O pins does the ATSAMR35J18B-I/7JX provide?
The ATSAMR35J18B-I/7JX provides 27 programmable general-purpose I/O pins, as confirmed in the Configuration Summary (DS70005356C-page 7) and Pin Placement diagram (DS70005356C-page 10). These pins support multiple peripheral functions-including SERCOM, TC/TCC, ADC, AC, and PTC-with flexible multiplexing controlled via PORT registers.
What LoRa® modulation modes and frequency bands are supported by the ATSAMR35J18B-I/7JX?
The ATSAMR35J18B-I/7JX supports LoRa®, (G)FSK, (G)MSK, and OOK modulation. Its transceiver covers three licensed-free ISM bands: 137–175 MHz, 410–525 MHz, and 862–1020 MHz. Band selection is configured in firmware; LoRaWAN™ regional parameters (e.g., EU868, US915) are implemented in certified stack layers, not hardware.
Is the ATSAMR35J18B-I/7JX pin-compatible with other SAM R35 variants such as ATSAMR35J17B-I/7JX?
Yes, all SAM R35 variants-including ATSAMR35J16B-I/7JX, ATSAMR35J17B-I/7JX, and ATSAMR35J18B-I/7JX-share identical 64-ball TFBGA (7JX) packaging and pinout. Differences are limited to Flash (64/128/256 KB), SRAM (8/16/32 KB), and LP SRAM (4/8 KB) capacities; no PCB redesign is needed when upgrading within the SAM R35 family.
ATSAMR35J18B-I/7JX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 64-TFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- TxRx + MCU
- RF Family/Standard:
- 802.15.4
- Protocol:
- LoRa™
- Modulation:
- FSK, GFSK, GMSK, MSK, OOK
- Frequency:
- 137MHz ~ 175MHz, 410MHz ~ 525MHz, 862MHz ~ 1.02GHz
- Data Rate (Max):
- -
- Power - Output:
- 20dBm
- Sensitivity:
- -148dBm
- Memory Size:
- 256kB Flash, 32kB SRAM
- Serial Interfaces:
- I2S, SPI, USART, USB
- GPIO:
- 27
- Voltage - Supply:
- 1.8V ~ 3.63V
- Current - Receiving:
- 14.8mA ~ 15.8mA
- Current - Transmitting:
- 32.5mA ~ 94.5mA
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 64-TFBGA (6x6)
ATSAMR35J18B-I/7JX FAQ
1.How can I place an order for ATSAMR35J18B-I/7JX through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMR35J18B-I/7JX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMR35J18B-I/7JX reliable?
The price and inventory of ATSAMR35J18B-I/7JX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMR35J18B-I/7JX is usually 5 days.
3.What payment methods are accepted for ATSAMR35J18B-I/7JX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMR35J18B-I/7JX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMR35J18B-I/7JX?
ATSAMR35J18B-I/7JX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMR35J18B-I/7JX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMR35J18B-I/7JX?
For technical support, including ATSAMR35J18B-I/7JX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMR35J18B-I/7JX requirements.
6.How does Aetrix verify that ATSAMR35J18B-I/7JX is sourced from the original manufacturer or authorized distributors?
All ATSAMR35J18B-I/7JX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMR35J18B-I/7JX meets industry standards.
7.What is the process for return or replacement of ATSAMR35J18B-I/7JX?
All ATSAMR35J18B-I/7JX units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMR35J18B-I/7JX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMR35J18B-I/7JX part is unused and in its original packaging.
Return procedure for ATSAMR35J18B-I/7JX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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