Microchip Technology ATSAMR35J18BT-I/7JX
- Part No.:
- ATSAMR35J18BT-I/7JX
- Manufacturer:
- Microchip Technology
- Category:
- RF Transceiver ICs
- Package:
- 64-TFBGA
- Datasheet:
-
ATSAMR35J18BT-I/7JX.pdf
- Description:
- IC RF TXRX+MCU 802.15.4 64TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,936
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ATSAMR35J18BT-I/7JX from Microchip Technology is an ultra-low-power System-in-Package (SiP) microcontroller integrating a 32-bit ARM Cortex-M0+ CPU (48 MHz), 256 KB Flash, 32 KB SRAM, 8 KB low-power SRAM, and a LoRa®/FSK UHF transceiver covering 137–1020 MHz bands with +20 dBm max output power. It targets battery-powered remote sensor nodes in industrial IoT and smart utility metering.
For engineers reviewing the ATSAMR35J18BT-I/7JX datasheet, ATSAMR35J18BT-I/7JX pinout, ATSAMR35J18BT-I/7JX application, or ATSAMR35J18BT-I/7JX equivalent, key selection considerations include LoRaWAN™-compliant sensitivity (−136 dBm), SleepWalking peripheral wake-up capability, 27 GPIOs in 6×6 mm TFBGA, RF transceiver integration without USB, and support for regional LoRa network stack compliance.
Technical Context
The ATSAMR35J18BT-I/7JX implements a dual-domain architecture: the MCU subsystem features ARM Cortex-M0+ with DFLL48M and FDPLL96M clock generators, configurable sleep modes (Idle, Standby, Backup), and SleepWalking peripherals enabling autonomous DMA-triggered wake-up. The integrated transceiver uses tri-band fractional-N PLL synthesis (137–175 MHz / 410–525 MHz / 862–1020 MHz) with LoRa®, (G)FSK, (G)MSK, and OOK modulation.
RF signal path includes RFI_HF/RFO_HF pins for high-frequency band operation, PA_BOOST terminal for +20 dBm output, and dedicated SERCOM4 interface (PB30/PB31/PC18/PC19) hardwired to the transceiver. No USB interface is present-distinguishing it from SAM R34 variants-making it suitable for compact, cost-sensitive, RF-first edge nodes where host connectivity is handled externally.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0+, 48 MHz max - delivers 2.46 CoreMark/MHz efficiency for deterministic real-time LoRa packet handling. |
| Memory | 256 KB Flash + 32 KB SRAM + 8 KB LP SRAM - supports full LoRaWAN stack, application firmware, and retained state during deep sleep. |
| Transceiver Bands | 137–175 MHz / 410–525 MHz / 862–1020 MHz - enables global deployment across EU868, US915, AS923, and CN470 regional plans. |
| LoRa Sensitivity | −136 dBm (LoRaWAN™ mode) - achieves >160 dB link budget for multi-kilometer range in rural deployments. |
| RF Output Power | +20 dBm (100 mW) at VDDANA > 2.4 V - meets ETSI EN 300 220 and FCC Part 15.247 limits without external PA. |
| Low-Power Operation | RX current = 17 mA (typical); Standby current < 1.5 µA - enables 10+ year battery life in periodic sensor reporting. |
| Package | 64-ball 6×6 mm TFBGA (7JX) - surface-mount compatible with automated assembly; 27 programmable I/O pins available. |
Pinout & Package
ATSAMR35J18BT-I/7JX is housed in a 64-ball 6×6 mm thin fine-pitch BGA (TFBGA) package designated 7JX, with 27 general-purpose I/O pins and dedicated RF/analog/power terminals. Pin functions are multiplexed via PORT configuration registers and validated per DS70005356C Figure 4-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PA_BOOST | RF Power Amplifier Enable | Active-high control for +20 dBm high-power output stage; requires external bias circuit per datasheet Section 5.4.2. |
| RFO_HF | High-Frequency RF Output | Primary antenna connection for 410–525 MHz and 862–1020 MHz bands; matched to 50 Ω impedance. |
| RFI_HF | High-Frequency RF Input | Receive path input for HF bands; internal LNA provides −136 dBm LoRaWAN sensitivity. |
| SERCOM4/PB30–PC19 | Transceiver Interface Bus | Dedicated SPI-like interface (clock, data in/out, chip select) connecting MCU core directly to transceiver baseband logic. |
| VDDANA | Analog Power Supply | 1.8–3.6 V supply for RF transceiver and ADC; must be filtered separately from digital rails to maintain SNR. |
Key Features
| Feature | Design Value |
|---|---|
| Tri-band LoRa Transceiver | Single SiP covers all major sub-GHz ISM bands - eliminates need for multiple SKUs or external RF switches. |
| SleepWalking Peripherals | ADC, TC, or SERCOM can autonomously sample, time, or receive data and wake CPU only on threshold/event - cuts average system current by >90%. |
| Hardware CRC-32 & AES | Offloads LoRaWAN frame integrity and security processing from CPU - reduces latency and flash footprint for certified stacks. |
| 12-bit 1 Msps ADC with Oversampling | Supports 13–16-bit effective resolution for analog sensor inputs (e.g., temperature, pressure) without external sigma-delta converter. |
| Event System with 12 Channels | Enables zero-CPU-latency peripheral-to-peripheral signaling (e.g., ADC completion → DMA trigger → SERCOM transmit) even in Standby mode. |
Applications
| Smart Utility Metering | Industrial Predictive Maintenance |
|---|---|
|
Use Scenario: Battery-powered gas/water meters transmitting hourly consumption data over 5–15 km rural LoRaWAN gateways. IC Role / Device Role / Timing Role: Primary SoC executing LoRaWAN Class C stack, managing secure OTA updates, and sampling metrology ADCs with hardware oversampling. Use Value: −136 dBm sensitivity and +20 dBm output enable single-hop coverage across wide-area distribution networks; 1.5 µA Standby current extends battery life beyond 15 years. |
Use Scenario: Vibration/temperature sensors mounted on motors or pumps in oil & gas facilities, reporting anomalies every 10 minutes. IC Role / Device Role / Timing Role: Edge inference node running lightweight ML models (via CMSIS-NN), using SleepWalking ADC to capture burst samples only when vibration thresholds are exceeded. Use Value: Event-driven wake-up and hardware-accelerated CRC/AES reduce active time per transmission to <200 ms - minimizing RF exposure and energy use in hazardous zones. |
| Agricultural Soil Monitoring | Asset Tracking in Logistics |
|
Use Scenario: Solar-charged soil moisture/nitrate probes deployed in remote fields, transmitting daily aggregated data via regional LoRaWAN. IC Role / Device Role / Timing Role: Integrated transceiver handles adaptive data rate (ADR) and channel hopping per LoRa Alliance spec; RTC triggers scheduled deep-sleep cycles. Use Value: Tri-band support allows same BOM across EU, US, and APAC deployments; LP SRAM retains calibration coefficients and network session keys during solar charging gaps. |
Use Scenario: Reusable cargo container trackers sending GPS location and door-open events via private LoRa network at warehouse gates. IC Role / Device Role / Timing Role: Dual-role device: transceiver manages LoRa uplink/downlink; MCU runs lightweight GNSS assist logic and tamper-detection state machine. Use Value: SERCOM4 hardwiring ensures deterministic transceiver latency (<50 µs interrupt response); 27 GPIOs support discrete door switch, LED status, and battery voltage monitoring. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LoRa sub-GHz SiP applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ATSAMR34J18BT-I/7JX | Includes full-speed USB 2.0 interface; identical MCU core, memory, and transceiver specs. | Required for USB-based firmware updates, PC-connected gateways, or dongle form factors. | Select when local USB host connectivity or field reprogramming via cable is mandatory - adds ~0.5 mm² PCB area for USB routing. |
| SEMTECH SX1276IMLTRT + STM32L072CZT6 | Discrete solution: separate LoRa transceiver IC and ultra-low-power MCU; no integrated SERCOM4 bus or SleepWalking. | Offers greater flexibility in RF layout, independent MCU/transceiver scaling, and legacy design reuse. | Choose when existing designs use SX1276 or require custom RF front-end tuning; increases BOM count and validation effort vs. single-SiP ATSAMR35J18BT-I/7JX. |
Compared with ATSAMR34J18BT-I/7JX, the ATSAMR35J18BT-I/7JX removes USB overhead to reduce leakage and simplify layout, while retaining identical RF performance and memory - making it optimal for sealed, maintenance-free endpoints. Versus discrete SX1276+STM32L072, the SiP integration cuts PCB area by 40%, eliminates inter-IC timing skew, and enables hardware-synchronized transceiver wake-up.
Availability
ATSAMR35J18BT-I/7JX is available at Aetrix Electronics and suitable for industrial IoT sensor nodes, smart utility metering, agricultural telemetry, and asset tracking requiring stable component supply across multi-year production cycles.
Supply support for ATSAMR35J18BT-I/7JX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and wireless solutions, with headquarters in Chandler, Arizona, and global design/support infrastructure.
The SAM R35 product line was designed specifically for ultra-low-power, long-range sub-GHz wireless applications - integrating LoRa transceivers and ARM Cortex-M0+ cores into a single SiP to eliminate RF design complexity and accelerate time-to-market for battery-operated edge devices.
FAQ
What is the maximum RF output power supported by the ATSAMR35J18BT-I/7JX?
The ATSAMR35J18BT-I/7JX supports up to +20 dBm (100 mW) output power in the high-frequency bands (410–525 MHz and 862–1020 MHz) when VDDANA exceeds 2.4 VDC. This complies with ETSI EN 300 220 and FCC Part 15.247 regulations without requiring external power amplification. Lower power modes (+17 dBm regulated, +13 dBm high-efficiency) are also available for optimized current consumption.
Does the ATSAMR35J18BT-I/7JX include USB functionality?
No, the ATSAMR35J18BT-I/7JX does not include USB functionality. It is the non-USB variant of the SAM R34/R35 family. The USB interface is present only in SAM R34 devices (e.g., ATSAMR34J18BT-I/7JX). The ATSAMR35J18BT-I/7JX relies on SERCOM interfaces (e.g., UART, SPI via SERCOM4) for host communication, reducing silicon area and standby current for RF-first applications.
How many GPIO pins are available on the ATSAMR35J18BT-I/7JX?
The ATSAMR35J18BT-I/7JX provides 27 programmable general-purpose I/O pins, as confirmed in the Configuration Summary (DS70005356C-page 7) and Pin Placement diagram (Figure 4-1). These pins support multiple peripheral functions including SERCOM, TC/TCC, ADC, AC, PTC, and external interrupts, with flexible multiplexing controlled via PORT configuration registers.
What LoRaWAN™-compliant sensitivity does the ATSAMR35J18BT-I/7JX achieve?
The ATSAMR35J18BT-I/7JX achieves −136 dBm sensitivity in LoRaWAN™ protocol-compliant modes (e.g., SF12, 125 kHz bandwidth), enabling robust reception under weak-signal conditions typical in deep-indoor or long-range rural deployments. This value is measured and specified in the Electrical Characteristics section (DS70005356C-page 39) and contributes to a maximum link budget of 168 dB.
Is the ATSAMR35J18BT-I/7JX pin-compatible with other SAM R35 variants?
Yes, all SAM R35 variants-including ATSAMR35J16BT-I/7JX, ATSAMR35J17BT-I/7JX, and ATSAMR35J18BT-I/7JX-share identical 64-ball 6×6 mm TFBGA (7JX) packaging and pinout. Differences are limited to Flash (64/128/256 KB), SRAM (8/16/32 KB), and LP SRAM (4/8 KB) configurations; no PCB layout change is required when upgrading memory density within the R35 family.
ATSAMR35J18BT-I/7JX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 64-TFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- TxRx + MCU
- RF Family/Standard:
- 802.15.4
- Protocol:
- LoRa™
- Modulation:
- FSK, GFSK, GMSK, MSK, OOK
- Frequency:
- 137MHz ~ 175MHz, 410MHz ~ 525MHz, 862MHz ~ 1.02GHz
- Data Rate (Max):
- -
- Power - Output:
- 20dBm
- Sensitivity:
- -148dBm
- Memory Size:
- 256kB Flash, 32kB SRAM
- Serial Interfaces:
- I2S, SPI, USART, USB
- GPIO:
- 27
- Voltage - Supply:
- 1.8V ~ 3.63V
- Current - Receiving:
- 14.8mA ~ 15.8mA
- Current - Transmitting:
- 32.5mA ~ 94.5mA
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 64-TFBGA (6x6)
ATSAMR35J18BT-I/7JX FAQ
1.How can I place an order for ATSAMR35J18BT-I/7JX through Aetrix?
Please submit a Request for Quotation (RFQ) for ATSAMR35J18BT-I/7JX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATSAMR35J18BT-I/7JX reliable?
The price and inventory of ATSAMR35J18BT-I/7JX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATSAMR35J18BT-I/7JX is usually 5 days.
3.What payment methods are accepted for ATSAMR35J18BT-I/7JX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATSAMR35J18BT-I/7JX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATSAMR35J18BT-I/7JX?
ATSAMR35J18BT-I/7JX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATSAMR35J18BT-I/7JX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATSAMR35J18BT-I/7JX?
For technical support, including ATSAMR35J18BT-I/7JX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATSAMR35J18BT-I/7JX requirements.
6.How does Aetrix verify that ATSAMR35J18BT-I/7JX is sourced from the original manufacturer or authorized distributors?
All ATSAMR35J18BT-I/7JX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATSAMR35J18BT-I/7JX meets industry standards.
7.What is the process for return or replacement of ATSAMR35J18BT-I/7JX?
All ATSAMR35J18BT-I/7JX units undergo pre-shipment inspection (PSI). If there is an issue with ATSAMR35J18BT-I/7JX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATSAMR35J18BT-I/7JX part is unused and in its original packaging.
Return procedure for ATSAMR35J18BT-I/7JX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ATSAMR35J18BT-I/7JX Tags

-
ESP32-D0WD-V3
Espressif Systems

-
ESP8266EX
Espressif Systems

-
ESP32-S3
Espressif Systems

-
NRF24L01P-R7
Nordic Semiconductor ASA

-
NRF24L01P-R
Nordic Semiconductor ASA

-
ESP32-U4WDH
Espressif Systems

-
DA14531-00000OG2
Renesas

-
ESP32-C6FH4
Espressif Systems

-
DA14531-00000FX2
Renesas

-
NRF24L01P-T
Nordic Semiconductor ASA

-
NRF52810-QCAA-R
Nordic Semiconductor ASA

-
ESP32-S3FN8
Espressif Systems
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

