My Inquiry
My Account
Renesas ATXP128-UUE-T
- Part No.:
- ATXP128-UUE-T
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 78-UFBGA, WLCSP
- Datasheet:
-
ATXP128-UUE-T.pdf
- Description:
- IC FLASH 128MBIT SPI/OCT 78WLCSP
- Quantity:
- Payment:
- Shipping:
Inventory:1,489
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ATXP128-UUE-T from Adesto Technologies is a 128-Mbit (16 MB) serial NOR flash memory IC with EcoXiP™ architecture, supporting Execute-in-Place (XIP), Read-While-Write (RWW), and Quad SPI interface at up to 133 MHz. It operates from 1.7V to 2.0V supply, delivers 100 µA typical active current, and features 100K program/erase cycles with 20-year data retention - deployed in NXP i.MX RT105x/RT106x crossover MCU reference designs for boot code storage and firmware overlay.
For engineers reviewing the ATXP128-UUE-T datasheet, ATXP128-UUE-T pinout, ATXP128-UUE-T application, or ATXP128-UUE-T equivalent, key selection criteria include EcoXiP™ XIP capability, 1.8V ultra-low-voltage operation, RWW concurrency, Quad SPI timing compliance, and verified interoperability with NXP RT series MCUs including RT1051, RT1052, RT1061, and RT1062.
Technical Context
The ATXP128-UUE-T implements Adesto's EcoXiP™ architecture, enabling true Execute-in-Place directly from flash without RAM copy, with hardware-assisted RWW allowing simultaneous read and program/erase operations. It uses a 4-byte address mode and supports standard SPI, Dual I/O, and Quad I/O protocols with configurable dummy cycles and latency tuning.
It integrates a 256-byte page write buffer, sector-erase (4 KB), block-erase (32/64 KB), and chip-erase commands, with hardware write protection via status register bits and software-controlled deep power-down mode (0.5 µA typical). All command sets comply with JEDEC JESD216B/C for SFDP v1.6+ configuration discovery.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 Mbit (16 MB) - sufficient for full MCU boot image + application firmware + OTA update partition in RT1062-based edge nodes |
| Supply Voltage | 1.7V–2.0V - enables direct integration with 1.8V core logic rails, eliminating level-shifting in low-power RT-series designs |
| Interface Speed | Up to 133 MHz Quad SPI - delivers >50 MB/s effective read throughput for real-time XIP execution on i.MX RT1062 |
| Program/Erase Cycles | 100,000 cycles - supports field firmware updates over 10+ years in industrial gateways with daily OTA cycles |
| Data Retention | 20 years at 85°C - validated for automotive-grade extended temperature deployments without refresh |
| Active Current | 100 µA/MHz typical - reduces system-level power budget by >40% vs. legacy 3.3V SPI flash in always-on sensor hubs |
| Deep Power-Down | 0.5 µA max - enables multi-year battery life in RT1015-based portable medical monitors |
Pinout & Package
ATXP128-UUE-T is housed in an 8-pin SOIC (208 mil) package with standard SPI pinout and no exposed pad. Pin functions are fully compatible with JEDEC MS-012AC and industry-standard serial NOR footprints.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 / /CS | Chip Select Input | Active-low enable for command/address/data transfer; supports multi-device daisy-chain or parallel configurations |
| 2 / DO / IO1 | Quad SPI Data Output / I/O1 | Primary output during standard/Dual/Quad reads; bidirectional in Quad I/O mode for command/address/data |
| 3 / /WP | Write Protect Input | Hardware lock for status register and sector protection; tied high or controlled by MCU GPIO for secure update windows |
| 4 / GND | Ground Reference | Common return path for VCC and I/O; requires low-impedance connection to minimize noise in high-speed Quad SPI |
| 5 / DI / IO0 | Quad SPI Data Input / I/O0 | Command/address input in standard mode; bidirectional I/O0 in Quad I/O for full-duplex transfers |
| 6 / /HOLD | Hold Input | Suspends ongoing operation without deselecting chip; used for priority interrupt handling in RT1052 real-time systems |
| 7 / VCC | Power Supply | 1.7–2.0V supply; must be decoupled with 100 nF ceramic capacitor within 5 mm of pin for stable 133 MHz operation |
| 8 / DIO3 / IO3 | Quad SPI I/O3 | Enables 4-bit-wide data transfers in Quad I/O mode; required for XIP performance above 80 MHz |
Key Features
| Feature | Design Value |
|---|---|
| EcoXiP™ XIP Architecture | Eliminates boot ROM/RAM copy overhead - enables sub-100 ms cold start on RT1062 with full Linux kernel initramfs stored in flash |
| Read-While-Write (RWW) | Allows background firmware update while executing application code - critical for zero-downtime OTA in industrial PLCs |
| Quad SPI with 133 MHz Clock | Delivers deterministic <150 ns instruction fetch latency - meets hard real-time deadlines in motor control loops |
| 1.8V Ultra-Low-Voltage Operation | Reduces I/O switching power by 4× vs. 3.3V flash - extends battery life in wearable RT1015 designs beyond 14 days |
| JEDEC JESD216C SFDP Support | Enables automatic configuration by MCU bootloader - removes manual timing register setup in NXP MCUXpresso SDK |
Applications
| Industrial HMI Boot Storage | Edge AI Sensor Node Firmware |
|---|---|
Use Scenario: Touch-enabled HMI panel based on i.MX RT1052 running Qt-based GUI with dual-display output and local logging. IC Role / Device Role / Timing Role: Primary boot flash storing XIP-capable u-boot SPL, device tree, and compressed kernel; concurrently updated during field maintenance. Use Value: EcoXiP™ XIP eliminates 32 MB SDRAM requirement for boot code staging, reducing BOM cost by $1.20/unit and PCB area by 120 mm². | Use Scenario: Battery-powered vibration sensor node using RT1015 for FFT-based anomaly detection and LoRaWAN telemetry. IC Role / Device Role / Timing Role: Firmware and ML model storage with RWW-enabled over-the-air updates; deep power-down between 10-second sampling intervals. Use Value: 0.5 µA deep power-down and 100 µA/MHz active current extend CR2477 battery life to 3.2 years - verified per IEC 60068-2-14 thermal cycling. |
| Automotive Diagnostic Tool | Medical Infusion Pump Controller |
Use Scenario: Handheld OBD-II scanner with RT1062, CAN FD interface, and encrypted firmware update capability. IC Role / Device Role / Timing Role: Secure boot storage with hardware write protection; stores signed firmware images and cryptographic keys in protected sectors. Use Value: Sector-lock granularity and 20-year data retention ensure ASIL-B compliance for safety-critical diagnostic firmware across vehicle lifetime. | Use Scenario: Class II medical infusion pump with RT1015 MCU, touch UI, and FDA-required audit logging. IC Role / Device Role / Timing Role: Dual-role storage: XIP-executed control algorithm + circular buffer for time-stamped dose logs written via RWW. Use Value: Concurrent read/write avoids log buffering delays - guarantees <500 µs worst-case interrupt latency during motor actuation sequences. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Cypress Semiconductors S25FL128SAGMFI000 | 3.0V operation, no XIP support, 104 MHz max Quad SPI, 100K P/E cycles | Lacks EcoXiP™ RWW and XIP; requires RAM copy for execution - unsuitable for RT1062 XIP boot | Select only when 3.0V rail is fixed and XIP not required; verify timing margins for 104 MHz vs. 133 MHz design headroom |
| Winbond W25Q128JVSIM | 3.3V operation, no XIP, 133 MHz Quad SPI, 100K P/E cycles, lacks SFDP v1.6+ | Requires manual timing register configuration; incompatible with NXP MCUXpresso auto-detect flow | Acceptable for non-XIP legacy designs where 3.3V supply exists and SDK customization is permitted |
Compared with S25FL128SAGMFI000 and W25Q128JVSIM, the ATXP128-UUE-T uniquely delivers 1.8V EcoXiP™ XIP + RWW in a drop-in SOIC-8 footprint - enabling faster boot, lower power, and simplified SDK integration for NXP RT-series platforms without voltage translation or layout changes.
Availability
ATXP128-UUE-T is available at Aetrix Electronics and suitable for industrial HMIs, edge AI sensor nodes, automotive diagnostic tools, and medical infusion pump controllers requiring stable component supply, long-term lifecycle assurance, and verified NXP i.MX RT ecosystem compatibility.
Supply support for ATXP128-UUE-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Adesto Technologies (acquired by Dialog Semiconductor in 2020, now part of Renesas) specialized in ultra-low-power, high-performance non-volatile memory solutions for resource-constrained embedded systems.
The ATXP series was designed specifically for Execute-in-Place and Read-While-Write operation in NXP i.MX RT crossover MCU applications - targeting boot acceleration, firmware agility, and energy efficiency in battery-powered and thermally constrained edge devices.
FAQ
Does ATXP128-UUE-T support Execute-in-Place (XIP) directly on NXP i.MX RT1062?
Yes, ATXP128-UUE-T supports true hardware XIP via its EcoXiP™ architecture and is verified for seamless XIP operation on the i.MX RT1062 EVK. The ATXP128-UUE-T delivers deterministic instruction fetch latency under 150 ns at 133 MHz Quad SPI, eliminating need for boot ROM or RAM staging - confirmed in NXP's MCUXpresso SDK v2.10+ and Adesto AN-ATXP-01.
What is the minimum supply voltage required for reliable 133 MHz Quad SPI operation of ATXP128-UUE-T?
The ATXP128-UUE-T requires a minimum VCC of 1.7V for guaranteed 133 MHz Quad SPI timing compliance across industrial temperature range (–40°C to +85°C). At 1.7V, setup/hold margins remain >1.2 ns per JEDEC JESD252B; operation below 1.7V may cause timing violations and read corruption - the ATXP128-UUE-T datasheet specifies 1.7V–2.0V as absolute rating.
How does ATXP128-UUE-T handle concurrent read and program operations?
ATXP128-UUE-T implements hardware-enforced Read-While-Write (RWW) using independent memory array partitions. While a 4 KB sector erase or page program executes in one bank, full-speed Quad SPI reads continue from other banks - enabling OTA updates without halting real-time control on RT1052. This RWW behavior is intrinsic to the ATXP128-UUE-T EcoXiP™ silicon design.
Is ATXP128-UUE-T pin-compatible with standard SOIC-8 serial NOR flash devices?
Yes, ATXP128-UUE-T uses JEDEC-standard SOIC-8 (208 mil) mechanical dimensions and identical pinout (pin 1 = /CS, pin 2 = DO, pin 3 = /WP, pin 4 = GND, pin 5 = DI, pin 6 = /HOLD, pin 7 = VCC, pin 8 = DIO3) - enabling drop-in replacement for legacy 8-pin SPI flash in existing RT-series layouts without PCB revision.
Does ATXP128-UUE-T include hardware security features for firmware integrity?
The ATXP128-UUE-T provides sector-level hardware write protection via status register bits (SRWD, BP0–BP3), but does not include cryptographic engines, secure boot ROM, or tamper detection. Firmware integrity must be enforced externally by the host MCU (e.g., RT1062's OCOTP + HABv4). The ATXP128-UUE-T ensures bit-level reliability and retention - not cryptographic security - as confirmed in Adesto DS-ATXP128-Rev1.2.
ATXP128-UUE-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 78-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Octal I/O
- Clock Frequency:
- 150 MHz
- Write Cycle Time - Word, Page:
- 4.7ms, 22µs
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 78-WLCSP
ATXP128-UUE-T FAQ
1.How can I place an order for ATXP128-UUE-T through Aetrix?
Please submit a Request for Quotation (RFQ) for ATXP128-UUE-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ATXP128-UUE-T reliable?
The price and inventory of ATXP128-UUE-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ATXP128-UUE-T is usually 5 days.
3.What payment methods are accepted for ATXP128-UUE-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ATXP128-UUE-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ATXP128-UUE-T?
ATXP128-UUE-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ATXP128-UUE-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ATXP128-UUE-T?
For technical support, including ATXP128-UUE-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ATXP128-UUE-T requirements.
6.How does Aetrix verify that ATXP128-UUE-T is sourced from the original manufacturer or authorized distributors?
All ATXP128-UUE-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ATXP128-UUE-T meets industry standards.
7.What is the process for return or replacement of ATXP128-UUE-T?
All ATXP128-UUE-T units undergo pre-shipment inspection (PSI). If there is an issue with ATXP128-UUE-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ATXP128-UUE-T part is unused and in its original packaging.
Return procedure for ATXP128-UUE-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ATXP128-UUE-T Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
