Infineon Technologies BF1009SRE6327HTSA1

Overview

BF1009SRE6327HTSA1 from Infineon Technologies is a silicon N-channel tetrode MOSFET designed for low-noise, high-gain RF input stages up to 1 GHz. It features integrated dual-gate biasing (G1/G2), operates at 9 V drain-source voltage, delivers 22 dB typical power gain at 800 MHz, and achieves 1.4 dB typical noise figure - deployed in VHF/UHF receiver front-ends and AGC-controlled amplifiers.

For engineers reviewing the BF1009SRE6327HTSA1 datasheet, BF1009SRE6327HTSA1 pinout, BF1009SRE6327HTSA1 application, or BF1009SRE6327HTSA1 equivalent, key selection criteria include its dual-gate transconductance control (g_fs = 30 mS), gate2 pinch-off voltage (V_G2S(p) = 0.9 V), self-biased operating current (I_DSO = 13 mA), and SOT143R package thermal resistance (R_thchs ≤ 370 K/W).

Technical Context

This tetrode MOSFET uses independent gate control: Gate 1 serves as high-impedance RF input with C_g1ss = 2.1 pF (typ.), while Gate 2 provides DC bias and gain control (ΔG_p = 50 dB range). Its structure enables stable low-noise amplification without external bias components.

Thermal design relies on solder-point referenced channel-to-sink resistance (R_thchs ≤ 370 K/W) under T_S ≤ 76 °C, and electrical safety is defined by V_(BR)DS = 12 V, ±V_(BR)G2SS = 12 V, and strict ESD handling requirements per AEC-Q101 Grade 2.

Key Specifications

Pinout & Package

SOT143R package: 4-pin plastic surface-mount package with reverse-bar marking, 1.3 mm × 1.7 mm footprint, 0.95 mm height, and exposed drain pad for thermal conduction.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-gate RF amplifier applications.

Compared with BFP181RH6327XTSA1 and NE3210M03, BF1009SRE6327HTSA1 uniquely combines integrated biasing, 50 dB gain control range, and AEC-Q101 qualification - making it optimal for cost-sensitive, space-constrained automotive and consumer RF receivers below 1 GHz.

Availability

BF1009SRE6327HTSA1 is available at Aetrix Electronics and suitable for FM radio receivers, automotive keyless entry systems, UHF wireless microphones, and ISM-band sensor hubs requiring stable component supply across production lifecycles.

Supply support for BF1009SRE6327HTSA1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies AG is a German semiconductor manufacturer specializing in power management, RF, and automotive ICs, with global R&D and manufacturing infrastructure.

BF1009SRE6327HTSA1 belongs to Infineon's RF transistor product line, engineered specifically for low-noise, gain-controllable amplification in sub-1 GHz wireless receivers - emphasizing integration, reliability, and automotive qualification.

FAQ

What is the recommended PCB layout for BF1009SRE6327HTSA1 to maintain RF stability?

Use a solid ground plane beneath the SOT143R package with direct vias to inner layers under pins 1 (S) and 2 (D). Keep Gate 1 (pin 4) trace short and isolated; route Gate 2 (pin 3) with controlled impedance if used for analog gain control. Avoid routing RF traces near Gate 2 to prevent coupling.

Can Gate 1 be DC-biased externally, or must it remain at AC-coupled potential?

Gate 1 must remain AC-coupled and unbiased in active mode. The datasheet explicitly warns against applying external DC voltage to Gate 1 during operation, as it degrades noise performance and risks device instability due to unintended bias shift.

How does the gain control range (ΔG_p) behave across frequency?

ΔG_p = 50 dB is specified at 800 MHz. At 200 MHz, |S21|² variation remains ≥45 dB; at 1 GHz, it drops to ~35 dB. This roll-off is inherent to the tetrode's interelectrode capacitance and is documented in Figure 4 of the datasheet.

Is the SOT143R package pinout identical to SOT143, or are there layout differences?

SOT143R has reversed pin numbering: pin 1 = S (same), but pin 2 = D (vs. pin 2 = D in SOT143), pin 3 = G2 (vs. G2), pin 4 = G1 (vs. G1) - however, the physical orientation includes a reverse bar marking, requiring mirrored PCB footprint placement versus standard SOT143.