NXP Semiconductors BLD6G22LS-50,112
- Part No.:
- BLD6G22LS-50,112
- Manufacturer:
- NXP Semiconductors
- Category:
- Single FETs, MOSFETs
- Package:
- SOT-1130B
- Datasheet:
-
BLD6G22LS-50,112.pdf
- Description:
- RF MOSFET LDMOS 28V CDFM4
- Quantity:
- Payment:

- Shipping:

Inventory:30
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
BLD6G22LS-50 from NXP Semiconductors is a fully integrated Doherty RF power transistor based on GEN6 LDMOS technology, designed for W-CDMA base station amplifiers operating at 2110–2170 MHz. It delivers 8 W average output power, 14 dB power gain, and 40 % drain efficiency under 2-carrier W-CDMA conditions (PAR = 8.3 dB), with integrated main/peak amplifiers, input splitter, and output combiner in a single ceramic package.
For engineers reviewing the BLD6G22LS-50 datasheet, BLD6G22LS-50 pinout, BLD6G22LS-50 application, or BLD6G22LS-50 equivalent, this device supports high-efficiency digital pre-distortion (DPD) amplifier designs requiring rugged load mismatch tolerance (VSWR = 10:1), independent peak bias control down to 0 V, and thermally optimized operation at Tj ≤ 200 °C.
Technical Context
The BLD6G22LS-50 implements an asymmetrical Doherty architecture with a 90° phase-shifted input splitter and integrated passive combiner, enabling high efficiency across back-off regions. Its dual-gate structure allows independent DC biasing of main (VGS(amp)main) and peak (VGS(amp)peak) amplifiers - with peak gate voltage adjustable from −0.5 V to +13 V, including 0 V for Class-B-like turn-on.
Thermally, it features a low Rth(j-case) of 1.9 K/W at 8 W output and 80 °C case temperature, supported by a flanged ceramic SOT1130B package with direct thermal path to heatsink. The device is internally matched for 50 Ω systems and includes integrated ESD protection per IEC 61000-4-2.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Frequency Range | 2110–2170 MHz - Optimized for W-CDMA Band I uplink/downlink infrastructure applications. |
| Average Output Power | 8 W - Delivered under 2-carrier W-CDMA (PAR = 8.3 dB, 0.01 % CCDF), enabling multi-user DPCH support. |
| Power Gain | 14 dB - Measured at 8 W average output, reducing driver stage complexity and cascaded noise figure. |
| Drain Efficiency | 40 % - Achieved at 8 W average output and 28 V drain supply, lowering thermal load and power supply requirements. |
| ACPR | −30 dBc - Adjacent channel power ratio at 5 MHz offset, meeting 3GPP W-CDMA spectral mask requirements. |
| Output at 3 dB Compression | 55 W - Peak pulsed CW capability confirms headroom for transient signal peaks without saturation. |
| Junction Temperature Limit | 200 °C - Enables reliable operation under sustained high-power Doherty mode with proper heatsinking. |
Pinout & Package
The BLD6G22LS-50 uses the earless flanged ceramic SOT1130B package (17.12 × 9.91 mm footprint, 3.30 mm height), optimized for RF thermal management and PCB mounting without flange screws. It features five terminals: drain, gate + main bias, source, no-connect, and peak bias.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Drain | High-current RF output node connected to internal main and peak amplifier drains; requires low-inductance RF grounding and heatsinking. |
| 2 | Gate + Bias Main | Combined RF input and DC bias path for main amplifier; must be decoupled with RF choke and bypass capacitor. |
| 3 | Source | Common source reference for both main and peak amplifiers; tied directly to ground plane for minimal impedance return path. |
| 4 | n.c. | No internal connection - electrically isolated; must remain unconnected on PCB to avoid parasitic coupling. |
| 5 | Bias Peak | Dedicated DC bias terminal for peak amplifier gate; enables independent adjustment from −0.5 V to +13 V for optimal Doherty alignment. |
Key Features
| Feature | Design Value |
|---|---|
| Fully integrated Doherty architecture | Includes monolithic 90° input splitter, main/peak LDMOS cells, and passive output combiner - eliminates external couplers and reduces board area by >40 %. |
| Independent peak bias control | Peak amplifier gate biased via Pin 5 (VGS(amp)peak = 0 V typical), enabling precise Doherty knee tuning without altering main amplifier quiescent point. |
| Ruggedness under mismatch | Guaranteed operation into VSWR = 10:1 at all phases (2140 MHz, 28 V, 8 W), eliminating need for external circulators in macrocell deployments. |
| Internally matched design | Input and output impedances pre-tuned for 50 Ω systems across 2110–2170 MHz - simplifies matching network to two external capacitors and one inductor. |
| ESD protection | Integrated HBM ESD structure rated per JEDEC JS-001 - withstands ≥2 kV human-body model without external protection diodes. |
Applications
| Macrocell Base Station Transmitter | W-CDMA Remote Radio Head (RRH) |
|---|---|
Use Scenario: High-power outdoor cellular base station transmitting two 5-MHz W-CDMA carriers in Band I (2110–2170 MHz) with digital pre-distortion. IC Role / Device Role / Timing Role: Final-stage Doherty RF power amplifier delivering 8 W average output with 40 % efficiency and −30 dBc ACPR. Use Value: Reduces system power consumption by 18 % versus Class-AB alternatives while maintaining linearity for 64-DPCH modulation. |
Use Scenario: Compact remote radio head deployed on cell tower with constrained thermal envelope and strict EMI limits. IC Role / Device Role / Timing Role: Integrated Doherty PA enabling single-chip 2140 MHz amplification with embedded bias control and thermal feedback interface. Use Value: Eliminates discrete splitter/combiner components, cutting bill-of-materials cost by $3.20/unit and improving assembly yield. |
| Multi-Carrier DPD Test Bench | Small Cell Outdoor Unit |
Use Scenario: Lab validation platform for adaptive DPD algorithms using 2-carrier W-CDMA signals with variable PAR and carrier spacing. IC Role / Device Role / Timing Role: Reference Doherty amplifier with tunable peak bias (Pin 5) for real-time knee-point characterization and memory effect analysis. Use Value: Enables repeatable ACPR vs. VGS(amp)peak sweeps from 0 V to 0.8 V - critical for DPD coefficient extraction. |
Use Scenario: Low-footprint outdoor small cell unit serving dense urban areas with co-located LTE/W-CDMA bands. IC Role / Device Role / Timing Role: High-ruggedness final PA supporting 10:1 VSWR survivability during antenna retuning or environmental icing events. Use Value: Avoids field failures due to reflected power transients, extending mean time between failures (MTBF) by 3.7× over non-ruggedized PAs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Doherty RF power amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| BLD6G22L-50 | SOT1130A package with flange and two mounting holes; identical RF specs and pinout except mechanical mounting interface. | Requires screw-mounted heatsink; preferred for high-vibration macrocell cabinets where mechanical stability is critical. | Select BLD6G22L-50 when forced-air cooling and rigid chassis mounting are available; BLD6G22LS-50 suits clip-fit or thermal-pad assemblies. |
| MRF6VP2600HR5 | 600 W GaN HEMT; higher P3dB (600 W), wider bandwidth (1805–2200 MHz), but requires external Doherty combiner and separate bias control. | Targets high-power macrocells (>100 W avg); lacks monolithic integration - increases layout complexity and calibration effort. | Choose MRF6VP2600HR5 only when scaling beyond 10 W average output; BLD6G22LS-50 provides lower-risk, drop-in-ready Doherty solution at 8 W. |
Compared with BLD6G22L-50, the BLD6G22LS-50 offers identical electrical performance in a flangeless SOT1130B package for simplified thermal interface, while MRF6VP2600HR5 delivers higher power at the cost of full external Doherty implementation - making BLD6G22LS-50 optimal for cost-sensitive, space-constrained 8 W W-CDMA RRH designs.
Availability
BLD6G22LS-50 is available at Aetrix Electronics and suitable for macrocell base stations, remote radio heads, DPD test benches, and outdoor small cell units requiring stable component supply and long-term lifecycle support.
Supply support for BLD6G22LS-50 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and communications markets, with over 50 years of RF power expertise.
The BLD6G22LS-50 belongs to NXP's GEN6 LDMOS Doherty transistor family, engineered specifically for energy-efficient, digitally predistorted W-CDMA infrastructure amplifiers operating in the 2.1 GHz band.
FAQ
What is the recommended gate bias voltage for the main amplifier in BLD6G22LS-50?
The BLD6G22LS-50 specifies a typical gate-source quiescent voltage (VGSq) of 2.05 V at VDS = 28 V and IDq = 170 mA for the main amplifier. This value is derived from the device's threshold voltage range (1.4–2.4 V) and ensures stable Class-AB operation with optimal linearity and efficiency. Always verify bias using production circuit conditions per Table 7 of the datasheet.
Does BLD6G22LS-50 require external input/output matching networks?
Yes, the BLD6G22LS-50 is internally matched but still requires external matching components to achieve optimal 50 Ω interface across 2110–2170 MHz. Typical application circuits use one series inductor and two shunt capacitors on input/output - as shown in Figure 13 and Table 10 of the datasheet - to fine-tune ZS and ZL per load-pull data in Table 9.
How does the peak amplifier bias (Pin 5) affect BLD6G22LS-50 linearity?
Varying VGS(amp)peak on Pin 5 from 0 V to 0.8 V directly controls the Doherty amplifier's load modulation and knee point. At 0 V, peak conduction begins precisely at compression onset, maximizing efficiency; increasing voltage shifts knee earlier, trading efficiency for improved ACPR at medium power levels - as demonstrated in Figures 8–12 of the BLD6G22LS-50 datasheet.
Is BLD6G22LS-50 RoHS compliant?
Yes, the BLD6G22LS-50 complies with Directive 2002/95/EC (RoHS) and contains no lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB), or polybrominated diphenyl ethers (PBDE). Full compliance documentation is available in NXP's product change notifications and material declarations.
What thermal interface material is recommended for BLD6G22LS-50?
For the SOT1130B package, NXP recommends a thermally conductive elastomeric pad (e.g., Parker Chomerics CHO-THERM 3200) or silicone-based thermal grease (e.g., Dow Corning TC-5022) with thermal conductivity ≥1.5 W/m·K. Mounting pressure should be 35–65 psi to ensure uniform contact without cracking the ceramic body, per Package Outline Figure 15.
BLD6G22LS-50,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- SOT-1130B
- Packaging:
- Tray
- Product Status:
- Obsolete
- Technology:
- LDMOS
- Configuration:
- Dual, Common Source
- Frequency:
- 2.14GHz
- Gain:
- 14dB
- Voltage - Test:
- 28 V
- Current Rating (Amps):
- 10.2A
- Noise Figure:
- -
- Current - Test:
- 170 mA
- Power - Output:
- 8W
- Voltage - Rated:
- 65 V
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- CDFM4
BLD6G22LS-50,112 FAQ
1.How can I place an order for BLD6G22LS-50,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for BLD6G22LS-50,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for BLD6G22LS-50,112 reliable?
The price and inventory of BLD6G22LS-50,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for BLD6G22LS-50,112 is usually 5 days.
3.What payment methods are accepted for BLD6G22LS-50,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for BLD6G22LS-50,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for BLD6G22LS-50,112?
BLD6G22LS-50,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your BLD6G22LS-50,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for BLD6G22LS-50,112?
For technical support, including BLD6G22LS-50,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your BLD6G22LS-50,112 requirements.
6.How does Aetrix verify that BLD6G22LS-50,112 is sourced from the original manufacturer or authorized distributors?
All BLD6G22LS-50,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that BLD6G22LS-50,112 meets industry standards.
7.What is the process for return or replacement of BLD6G22LS-50,112?
All BLD6G22LS-50,112 units undergo pre-shipment inspection (PSI). If there is an issue with BLD6G22LS-50,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The BLD6G22LS-50,112 part is unused and in its original packaging.
Return procedure for BLD6G22LS-50,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
BLD6G22LS-50,112 Tags

-
3SK294(TE85L,F)
Toshiba Semiconductor and Storage
-
SAV-551+
Mini-Circuits

-
TAV2-501+
Mini-Circuits

-
CE3514M4-C2
CEL

-
AFT05MS004NT1
NXP USA Inc.
-
SAV-541+
Mini-Circuits

-
CE3512K2-C1
CEL

-
AFM907NT1
NXP Semiconductors

-
SKY65050-372LF
Skyworks Solutions Inc.

-
CE3520K3-C1
CEL

-
AFT09MS007NT1
NXP USA Inc.

-
AFT09MS015NT1
NXP USA Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
