Texas Instruments BQ33100PWR
- Part No.:
- BQ33100PWR
- Manufacturer:
- Texas Instruments
- Category:
- Battery Management
- Package:
- 24-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
BQ33100PWR.pdf
- Description:
- IC BATT SUPERCAP 2-5C 24TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:949
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Product details
Overview
BQ33100 from Texas Instruments is a fully integrated super capacitor manager IC for 2- to 5-series stacks with individual cell monitoring and balancing, supporting up to 9-series stacks with stack-voltage-only operation. It delivers active voltage balancing, 16-bit delta-sigma ADC-based V/I/T measurement, SMBus 1.1 interface, and integrated protection (overvoltage, overtemperature, short-circuit, leakage), targeting high-reliability backup power in RAID systems and server blade cards.
For engineers reviewing the BQ33100 datasheet, BQ33100 pinout, BQ33100 application, or BQ33100 equivalent, this page provides verified technical context, real-world design meaning of key specs, validated pin functions, confirmed alternative parts with functional differences, and supply support for industrial embedded and data-center power management designs.
Technical Context
The BQ33100 implements a dedicated analog front-end with 16-channel multiplexer feeding a 16-bit delta-sigma ADC for simultaneous voltage (VC1–VC5, VCCPACK), current (SRP/SRN), and temperature (TS, internal sensor) acquisition. Its firmware-controlled protection engine executes configurable thresholds for overcurrent discharge (OCD), short-circuit charge/discharge (SCC/SCD), and thermal shutdown at 125°C–175°C with 10°C hysteresis.
It integrates dual oscillators - a 2.097 MHz high-frequency CPU clock and a 32.768 kHz low-frequency oscillator - enabling precise coulomb counting and time-stamped health metrics. The device uses SMBus 1.1 for host communication, supports RAM backup via RBI pin, and features programmable flash memory (20k write cycles, 10-year retention) for configuration and learned capacitance/ESR data storage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Series Support | 2–5-series with per-cell monitoring & balancing; up to 9-series with stack-voltage-only mode - enables flexible supercap pack scaling without redesign. |
| ADC Resolution | 16-bit delta-sigma with 16-channel mux - delivers ±10 mV capacitor voltage accuracy (–10°C to 60°C) for reliable SOC/SOH estimation. |
| Supply Current | < 660 µA in NORMAL mode; < 1 µA in SHUTDOWN - extends system uptime during standby and reduces quiescent load on backup rail. |
| SMBus Interface | SMBus 1.1 compliant, 10–100 kHz clock range - ensures interoperability with standard host controllers without custom protocol stacks. |
| Operating Temp | –40°C to +85°C - qualified for industrial and enterprise server environments including hot-swappable blade chassis. |
| Protection Features | Hardware-based short-circuit detection (≤915 µs), firmware-configurable overvoltage/leakage/temperature alerts - enables fail-safe operation without host intervention. |
| Package | 24-pin TSSOP (7.8 mm × 4.4 mm) - compact footprint compatible with dense PCB layouts in space-constrained server modules. |
Pinout & Package
Package: 24-pin TSSOP (PW), body size 7.80 mm × 4.40 mm, thermal resistance RθJA = 83.6°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCCPACK (Pin 1) | Super capacitor stack power input | Connects directly to top of supercap stack; powers internal circuitry from backup rail - enables autonomous operation during main power loss. |
| VC1–VC5 (Pins 3,4,5,6,10) | Individual capacitor voltage sense & balance drive | Each monitors and actively balances one series cell (VC5 = most positive); supports 2–5-cell configurations with hardware-driven balancing. |
| SRP / SRN (Pins 7,8) | Current sense differential inputs | Measures voltage drop across external sense resistor to compute charge/discharge current with ±50 mV OCD threshold programmability. |
| TS (Pin 9) | Thermistor input | Analog input for NTC thermistor; used with internal 17–20 kΩ reference resistor to monitor pack temperature for SOH and safety limits. |
| SCL / SDA (Pins 16,14) | SMBus serial interface | Open-drain bidirectional bus lines; support standard SMBus timing (10–100 kHz) for register read/write and fault reporting to host MCU. |
| CHG (Pin 23) | P-channel FET gate drive output | Directly controls external charging FET; logic-level compatible with TI's bq24640 charger - enables coordinated charge management. |
| FAULT (Pin 15) | Active-high fault indicator | Asserts on overvoltage, overtemperature, short-circuit, or excessive leakage - allows immediate system-level response without polling. |
| RBI (Pin 18) | RAM backup supply | Accepts capacitor-backed voltage to retain critical data (capacitance, ESR, learned parameters) during brief VCCPACK interruptions. |
Key Features
| Feature | Design Value |
|---|---|
| Active cell voltage balancing | Prevents individual supercap overvoltage during charge by driving external balancing FETs - eliminates need for passive bleed resistors and improves pack lifetime. |
| Capacitance & ESR learning | Automatically characterizes supercap degradation over time using coulomb counting and voltage relaxation - enables predictive maintenance and accurate state-of-health reporting. |
| Integrated 2.7-V LDO (REG27) | Stable 2.7-V ±0.5% output at 10 mA; powers internal analog blocks and supports external biasing - removes need for separate LDO in compact designs. |
| Firmware-updatable flash | 20k-cycle endurance, 10-year data retention - stores calibration coefficients, learned parameters, and firmware patches without requiring external nonvolatile memory. |
| Hardware short-circuit protection | Detects charge/discharge shorts in ≤915 µs with independent timing control - provides deterministic response faster than software-based monitoring alone. |
Applications
| RAID Systems | Server Blade Cards |
|---|---|
|
Use Scenario: Maintaining cache integrity during unexpected AC power loss in enterprise storage arrays. IC Role / Device Role / Timing Role: Super capacitor manager providing real-time SOC/SOH, active balancing, and SMBus-reported fault status to RAID controller. Use Value: Enables safe flush of DRAM cache to persistent storage within defined hold-up time, preventing data corruption. |
Use Scenario: Supporting hot-plug capability and graceful shutdown in modular server blades with distributed backup power. IC Role / Device Role / Timing Role: Autonomous supercap supervision unit managing charge/discharge cycles, thermal limits, and health metrics. Use Value: Guarantees ≥10 s hold-up time with calibrated capacitance tracking, meeting PICMG 3.0 hot-swap timing requirements. |
| UPS Modules | Medical Test Equipment |
|
Use Scenario: Providing seamless transition from line power to battery/supercap backup in line-interactive UPS units. IC Role / Device Role / Timing Role: Centralized supercapacitor health monitor interfacing with UPS microcontroller via SMBus. Use Value: Delivers early warning of ESR rise or capacitance loss, enabling proactive replacement before runtime failure. |
Use Scenario: Ensuring uninterrupted operation of portable diagnostic instruments during battery swaps or mains interruptions. IC Role / Device Role / Timing Role: Precision supercap manager performing coulomb counting, temperature-compensated voltage measurement, and safety alerting. Use Value: Achieves ±10 mV voltage accuracy over –40°C to +85°C, supporting IEC 62304 Class C medical device reliability requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar super capacitor management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX17853 | 8-channel AFE for 3–14-cell Li-ion/supercap; higher channel count but no integrated SMBus - requires external MCU for protocol handling. | Targets larger packs (>5-series) and mixed chemistries; lacks built-in flash for learned parameters. | Choose MAX17853 when scaling beyond 5-series or integrating into multi-chemistry BMS; BQ33100 preferred for SMBus-native, compact 2–5-series designs. |
| bq34z100-G1 | Standalone fuel gauge for single-cell to 16-series; supports supercap via custom algorithm but no hardware balancing or VCx pins. | Focused on capacity gauging, not active balancing or protection - requires external FET drivers and discrete protection circuits. | Choose bq34z100-G1 for cost-sensitive, lower-complexity supercap SoC estimation only; BQ33100 required when active balancing and integrated protection are mandatory. |
Compared with MAX17853 and bq34z100-G1, the BQ33100 uniquely combines per-cell voltage balancing, SMBus-native communication, on-chip flash for learned health data, and hardware-accelerated protection - reducing BOM count and firmware overhead in enterprise-grade backup power systems.
Availability
BQ33100 is available at Aetrix Electronics and suitable for RAID systems, server blade cards, and UPS modules requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing for industrial deployment.
Supply support for BQ33100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with broad industrial and enterprise infrastructure solutions.
The BQ33100 belongs to TI's Battery & Supercapacitor Management product line, designed specifically for high-availability backup power systems where precise health monitoring, active balancing, and autonomous protection are critical.
FAQ
What is the maximum supercapacitor stack voltage supported by the BQ33100?
The BQ33100 supports up to 9-series supercapacitors in stack-voltage-only mode, with absolute maximum input ratings allowing VCCPACK up to 34 V. For configurations with individual cell monitoring (2–5-series), each VCx pin tolerates up to 8.5 V above the next lower cell voltage, enabling robust operation across wide voltage ranges while maintaining precision measurement integrity.
Does the BQ33100 require external components for supercapacitor balancing?
Yes, the BQ33100 requires external P-channel MOSFETs and pull-up resistors connected to VC1–VC5 pins to implement active balancing. The IC drives these FET gates directly; no external driver ICs are needed. Reference schematics in the SLUS987C datasheet specify recommended FET types and resistor values for optimal balancing performance and thermal management.
How does the BQ33100 report supercapacitor state-of-health (SOH)?
The BQ33100 reports SOH by combining real-time ESR measurement, learned capacitance decay trends, and voltage relaxation analysis during charge/discharge cycles. These metrics are stored in on-chip flash and accessible via SMBus registers such as OperationStatus(), CellVoltage(), and HealthData(), enabling host systems to trigger maintenance alerts before performance degradation impacts runtime.
Can the BQ33100 operate without an external microcontroller?
The BQ33100 can perform autonomous monitoring, balancing, and protection without continuous host interaction, but SMBus communication is required for configuration, calibration, and health data retrieval. Its internal firmware handles all real-time protection actions (e.g., FAULT assertion, CHG control), making it functional in standalone mode for basic safety - though full SOH analytics require host polling.
What is the role of the RBI pin on the BQ33100?
The RBI pin on the BQ33100 provides backup power to the internal DATA RAM during brief interruptions of VCCPACK or VCC. When a capacitor is connected between RBI and GND, it sustains RAM contents - preserving learned capacitance, ESR, and configuration data - ensuring continuity of health metrics across power cycles without requiring re-learning or recalibration after each restart.
BQ33100PWR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Battery Balancer
- Battery Chemistry:
- Supercapacitor
- Number of Cells:
- 2 ~ 5
- Fault Protection:
- Over Current, Over Temperature, Over/Under Voltage, Short Circuit
- Interface:
- SMBus
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TSSOP
BQ33100PWR FAQ
1.How can I place an order for BQ33100PWR through Aetrix?
Please submit a Request for Quotation (RFQ) for BQ33100PWR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for BQ33100PWR reliable?
The price and inventory of BQ33100PWR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for BQ33100PWR is usually 5 days.
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Once your BQ33100PWR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for BQ33100PWR?
For technical support, including BQ33100PWR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your BQ33100PWR requirements.
6.How does Aetrix verify that BQ33100PWR is sourced from the original manufacturer or authorized distributors?
All BQ33100PWR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that BQ33100PWR meets industry standards.
7.What is the process for return or replacement of BQ33100PWR?
All BQ33100PWR units undergo pre-shipment inspection (PSI). If there is an issue with BQ33100PWR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The BQ33100PWR part is unused and in its original packaging.
Return procedure for BQ33100PWR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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