Texas Instruments BQ4013YMA-70N

Overview

BQ4013YMA-70N from Texas Instruments is a 128 k × 8 (1,048,576-bit) nonvolatile SRAM with integrated lithium backup, 5-V operation, -40°C to +85°C industrial temperature range, and 70 ns access time. It functions as a standard CMOS SRAM during normal operation and automatically preserves data during power loss via internal power-fail detection and seamless switch-over to the onboard lithium cell - used in real-time clock modules, industrial PLCs, and metering systems requiring persistent memory without external battery management.

For engineers reviewing the BQ4013YMA-70N datasheet, BQ4013YMA-70N pinout, BQ4013YMA-70N application, or BQ4013YMA-70N equivalent, key selection considerations include its 32-pin DIP package, VPFD = 4.37 V (10% 5-V supply tolerance), tCER = 85 ms (3.3-V system) / 120 ms (5-V system), automatic write-protection on power-up/down, and 10-year data retention without external power.

Technical Context

The BQ4013YMA-70N integrates a 128 k × 8 SRAM core with dedicated power-fail detection circuitry that triggers at VPFD = 4.37 V (for 5-V ±10% systems), initiating automatic write-protection and switching to internal lithium backup before VCC drops below VSO ≈ 3 V. Its control logic ensures no data corruption during volatile-to-nonvolatile transitions.

All I/O operations follow industry-standard asynchronous SRAM timing: CE- and OE-controlled read cycles with tAA = 70 ns, WE-controlled write cycles with tWC = 70 ns, and high-impedance outputs during standby or power transition. The device requires no external components and maintains full compatibility with 1-Mb SRAM address/data bus protocols.

Key Specifications

Pinout & Package

32-pin dual in-line package (DIP), MA package type, through-hole mounting. Pin layout matches industry-standard 1-Mb SRAM footprint for drop-in replacement in legacy designs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar nonvolatile SRAM applications.

Compared with STK14CA8-70F3 and DS1248W-120+, the BQ4013YMA-70N uniquely delivers 70 ns 5-V performance in a pin-compatible 32-pin DIP package with VPFD tuned for ±10% 5-V supplies - making it the sole option for drop-in upgrades of legacy industrial controllers requiring minimal hardware revision.

Availability

BQ4013YMA-70N is available at Aetrix Electronics and suitable for industrial automation, smart metering, and medical diagnostics requiring stable component supply despite TI's OBSOLETE status - supported via verified legacy channel inventory and lifecycle-managed sourcing.

Supply support for BQ4013YMA-70N includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of experience in high-reliability memory solutions.

The BQ4013YMA-70N belongs to TI's bq nonvolatile SRAM product line, engineered specifically for mission-critical data retention in industrial and infrastructure applications where external battery management is impractical.

FAQ

What is the power-fail detect threshold voltage for BQ4013YMA-70N?

The BQ4013YMA-70N features a fixed power-fail detect (VPFD) threshold of 4.37 V (typical), optimized for 5-V systems with ±10% supply tolerance. This value is factory-trimmed and not user-adjustable. When VCC drops below VPFD, the device immediately enters write-protected mode and switches to internal lithium backup to preserve memory contents - a hardware-level function requiring no firmware intervention. The BQ4013YMA-70N maintains this behavior across its full -40°C to +85°C operating range.

Does BQ4013YMA-70N require external components for battery backup operation?

No, the BQ4013YMA-70N requires zero external components for full nonvolatile operation. Its integrated lithium coin cell is factory-installed and electrically isolated until the first application of VCC, after which internal circuitry automatically manages switchover between VCC and backup power. The device includes on-die voltage comparators, isolation FETs, and write-protection logic - eliminating the need for external supervisors, diodes, or charge controllers. This integration is confirmed in TI's SLUS121A datasheet Block Diagram and Functional Description sections.

Is BQ4013YMA-70N pin-compatible with standard 1-Mb SRAMs?

Yes, the BQ4013YMA-70N uses an industry-standard 32-pin DIP (MA package) footprint with identical pin assignments for A0–A16, DQ0–DQ7, CE, WE, OE, VCC, and VSS as JEDEC-compliant 1-Mb SRAMs. Pins 1 and 30 are NC, matching common 1-Mb layouts. This allows direct replacement in existing designs without PCB modification - provided the target system operates within the BQ4013YMA-70N's 5-V supply and -40°C to +85°C specifications.

How long does data retention last on BQ4013YMA-70N without external power?

The BQ4013YMA-70N guarantees ≥10 years of data retention without VCC, based on TI's characterization of the integrated lithium cell's self-discharge rate (<0.5% per year when isolated pre-activation). This retention period begins after the first power application activates the cell and accumulates only during actual VCC-absent intervals. TI specifies this in the General Description and Table 4 (5-V Power-Down/Power-Up), confirming it applies to the BQ4013YMA-70N variant per the Selection Guide and PART NUMBERING table.

What is the chip enable recovery time (tCER) for BQ4013YMA-70N?

The BQ4013YMA-70N has a maximum chip enable recovery time (tCER) of 120 ms in 5-V systems and 85 ms in 3.3-V systems, as specified in Tables 4 and 5 of the SLUS121A datasheet. This parameter defines the duration after VCC rises above VPFD during power-up when writes remain disabled to allow processor stabilization. For the BQ4013YMA-70N - a 5-V industrial-grade part - the 120 ms tCER applies, and this value is fixed by internal timing circuitry, not configurable via external signals or registers.