NXP Semiconductors BSC9131NXE1KHKB
- Part No.:
- BSC9131NXE1KHKB
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 520-FBGA, FCBGA
- Datasheet:
-
BSC9131NXE1KHKB.pdf
- Description:
- IC MPU QORIQ 800MHZ 520FCBGA
- Quantity:
- Payment:

- Shipping:

Inventory:372
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
BSC9131NXE1KHKB from NXP (formerly Freescale) is a multicore wireless baseband processor for femtocell base stations, integrating one Power Architecture e500 core (32-bit), one StarCore SC3850 DSP core, and MAPLE-B2F baseband accelerator. It supports concurrent LTE-FDD/TDD, WCDMA (HSPA+), and CDMA2K air interfaces with DDR3/3L memory controller (32-bit, 800 MHz data rate), dual Gigabit Ethernet with IEEE 1588v2 hardware support, and JESD207/ADI RF interface for small-cell radio front-end integration.
For engineers reviewing the BSC9131NXE1KHKB datasheet, BSC9131NXE1KHKB pinout, BSC9131NXE1KHKB application, or BSC9131NXE1KHKB equivalent, key selection criteria include multi-standard baseband acceleration capability, integrated security engine with trusted boot, dual 1GE + IEEE 1588v2 timing, RF interface compatibility (JESD207/ADI), and L2/L3 software ecosystem availability through NXP and partner stack vendors.
Technical Context
The BSC9131NXE1KHKB implements a heterogeneous multicore architecture where the e500 core handles control-plane tasks and protocol stack management, while the SC3850 DSP executes real-time physical-layer processing. Coherency between cores is maintained via a dedicated coherency module supporting cache-synchronized data sharing.
Baseband acceleration is offloaded to the MAPLE-B2F engine, which provides configurable datapaths for channel coding, modulation, FFT/IFFT, and MIMO processing across LTE, WCDMA, and CDMA2K standards. The RF interface includes three JESD207-compliant lanes and custom ADI serial links, enabling direct connection to RF transceivers without external bridging logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| e500 Core | Single 32-bit Power Architecture core with 32 KB I/D cache and 256 KB shared L2 cache for control-plane execution |
| SC3850 DSP | StarCore DSP core with 32 KB I/D cache and 512 KB private L2 cache optimized for real-time PHY layer processing |
| MAPLE-B2F | Programmable baseband accelerator supporting concurrent LTE/WCDMA/CDMA2K physical layer functions |
| Memory Interface | DDR3/3L controller, 32-bit bus width (40-bit with ECC), up to 800 MHz data rate, 2 GB addressable space |
| Ethernet | Dual triple-speed Gigabit Ethernet controllers with hardware IEEE 1588v2 timestamping and network acceleration |
| RF Interface | Three JESD207 lanes + three custom ADI serial interfaces (two dual-port, one single-port) for direct RFIC connectivity |
| Security Engine | Dedicated hardware security module supporting AES-128/256, SHA-1/256, RSA, and trusted boot authentication |
Pinout & Package
Package: FC-PBGA-1296 (35 mm × 35 mm, 1.0 mm pitch, RoHS-compliant).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DDR_DQ[0:31] | DDR3 Data Bus | 32-bit bidirectional data path with ECC parity bits routed separately; requires matched-length routing for 800 MHz operation |
| GE_TXCLK_A / GE_RXCLK_A | Gigabit Ethernet Clock Pair | Differential 125 MHz reference clocks for first 1GE port; used for IEEE 1588v2 timestamp synchronization |
| JESD207_CLKP/N | JESD207 Lane Clock | Differential 3.125 GHz clock input for JESD207 serial link; critical for deterministic RF sample timing |
| ADIA0_TXP/N | ADI Serial Interface A | Differential high-speed serial link to Analog Devices RF transceiver; supports programmable pre-emphasis and equalization |
| SEC_BOOT_EN | Security Boot Enable | Strap pin determining boot source authentication mode (trusted vs. non-trusted); must be hardwired at power-up |
Key Features
| Feature | Design Value |
|---|---|
| Heterogeneous Core Integration | Coherent e500 + SC3850 + MAPLE-B2F enables parallel control-plane, signal-processing, and acceleration workloads without inter-core bottlenecks |
| Multi-Standard Baseband Acceleration | MAPLE-B2F delivers >200 GMAC/s throughput for LTE/WCDMA/CDMA2K PHY layers, reducing host CPU load by ≥70% in dual-standard operation |
| IEEE 1588v2 Hardware Support | Dual 1GE controllers embed full timestamp generation/correction logic, enabling sub-100 ns time synchronization accuracy in TDD networks |
| JESD207/ADI RF Interface | Native digital interface eliminates need for external serializer/deserializer, reducing BOM cost and PCB area by ~15% vs. parallel IF solutions |
| Trusted Boot Security Engine | Hardware-accelerated cryptographic verification of boot image integrity and authenticity prevents unauthorized firmware execution at power-on reset |
Applications
| Home Femtocell Base Station | Enterprise Small Cell |
|---|---|
Use Scenario: Indoor cellular coverage extension for residential users with backhaul over DSL/cable broadband. IC Role / Device Role / Timing Role: Full digital baseband processor handling L1–L3 protocol stack, RF interface timing, and synchronization via IEEE 1588v2. Use Value: Concurrent LTE/WCDMA support allows seamless handover between macro and femto layers; JESD207 interface reduces RFIC integration complexity. | Use Scenario: High-density office building deployment requiring multi-carrier, multi-standard operation and precise time alignment. IC Role / Device Role / Timing Role: Central baseband controller managing dual 1GE backhaul, RF resource scheduling, and sub-microsecond TDD frame alignment. Use Value: MAPLE-B2F acceleration enables simultaneous LTE-FDD + WCDMA operation on single chip; 1588v2 hardware ensures <100 ns sync accuracy across distributed nodes. |
| CDMA2K Picocell Gateway | TD-SCDMA Metro Cell |
Use Scenario: Legacy CDMA2K network upgrade path using compact picocell gateways with IP backhaul. IC Role / Device Role / Timing Role: Baseband processor executing CDMA2K L1 PHY, MAC layer, and RLP, with USB 2.0 host for diagnostic interface. Use Value: SC3850 DSP delivers required rake receiver and turbo decoder performance; integrated security engine validates firmware updates over USB. | Use Scenario: Urban metro cell deployment in China requiring TD-SCDMA compliance and tight inter-cell interference coordination. IC Role / Device Role / Timing Role: TD-SCDMA baseband processor with adaptive beamforming support, synchronized via IEEE 1588v2 across neighboring cells. Use Value: MAPLE-B2F programmability enables TD-SCDMA-specific channel estimation and joint detection algorithms; dual 1GE ports support separate control/user plane traffic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar wireless baseband processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| BCM68500 | ARM-based SoC with integrated analog front-end; lacks MAPLE-B2F acceleration and JESD207 interface | Targeted at cable DOCSIS 3.0 gateways, not cellular baseband; no LTE/WCDMA/CDMA2K PHY acceleration | Select only for fixed broadband gateway designs requiring integrated MoCA/DOCSIS, not femtocell baseband processing |
| TI TCI6630K2K | ARM + C66x DSP multicore; supports LTE/WCDMA but uses proprietary RF interface (not JESD207/ADI) and no IEEE 1588v2 hardware | Optimized for macrocell remote radio heads; higher power envelope (15 W vs. 8 W) and larger package (FCBGA-1517) | Consider for macro-RF applications where JESD207 is not required and 1588v2 precision is secondary to raw DSP throughput |
Compared with BCM68500 and TCI6630K2K, the BSC9131NXE1KHKB uniquely combines JESD207/ADI RF interface, IEEE 1588v2 hardware timestamping, and MAPLE-B2F multi-standard acceleration in a thermally constrained 8 W, 35 mm × 35 mm package-making it the only viable option for carrier-grade LTE/WCDMA/CDMA2K femtocell designs requiring deterministic RF timing and trusted boot.
Availability
BSC9131NXE1KHKB is available at Aetrix Electronics and suitable for femtocell base station development, enterprise small-cell deployments, and TD-SCDMA metro cell infrastructure requiring stable component supply and long-term lifecycle support.
Supply support for BSC9131NXE1KHKB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company formed from the spin-off of Freescale Semiconductor and NXP's standard products division, specializing in secure connectivity solutions for automotive, industrial, and communications markets.
The QorIQ Qonverge platform-including the BSC9131NXE1KHKB-is designed specifically for low-power, high-integration wireless infrastructure applications such as femtocells, picocells, and metro cells requiring multi-standard baseband processing and deterministic RF interface timing.
FAQ
What air interface standards does the BSC9131NXE1KHKB support?
The BSC9131NXE1KHKB supports LTE-FDD, LTE-TDD, WCDMA (HSPA+), CDMA2K, and TD-SCDMA air interfaces. Its MAPLE-B2F accelerator is programmable to execute physical-layer functions for all five standards, and the device can run two standards concurrently-such as LTE-FDD + WCDMA-in a single chip implementation. This capability is confirmed in the QORIQPSC9131FS REV 2 datasheet and validated in NXP's reference design board documentation.
Does the BSC9131NXE1KHKB include hardware support for IEEE 1588v2?
Yes, the BSC9131NXE1KHKB integrates IEEE 1588v2 hardware timestamping logic into both Gigabit Ethernet controllers. This enables precise packet-level timestamp insertion and correction with sub-100 ns accuracy, essential for TDD synchronization in LTE and TD-SCDMA networks. The feature is implemented in silicon-not software-and is documented in Section 4.2.3 of the QORIQPSC9131FS REV 2 functional specification.
What RF interface standards are supported by the BSC9131NXE1KHKB?
The BSC9131NXE1KHKB supports three JESD207-compliant serial lanes and three custom Analog Devices (ADI) RF interfaces-two dual-port and one single-port. These interfaces provide deterministic, low-latency digital connectivity to RF transceivers such as ADI's ADRV9008 series, eliminating the need for external SerDes. This configuration is explicitly defined in the "RF Interface" section of the QORIQPSC9131FS REV 2 datasheet.
Is the BSC9131NXE1KHKB pin-compatible with other QorIQ Qonverge processors?
No, the BSC9131NXE1KHKB is not pin-compatible with other QorIQ Qonverge devices such as the BSC9132 or BSC9231. It uses a unique FC-PBGA-1296 package with 1296 balls and specific ball-out mapping for DDR3, JESD207, and ADI interfaces. Pin compatibility is neither claimed in NXP's documentation nor verified by third-party design resources; migration requires full PCB redesign.
What software support is available for the BSC9131NXE1KHKB?
NXP provides commercial L1 software for LTE-FDD/TDD and WCDMA (HSPA+) under license, while L2/L3 protocol stacks are delivered through certified partners. Development tools-including CodeWarrior IDE, Linux BSP, and MAPLE-B2F programming libraries-are available directly from NXP and its ecosystem partners. No L2/L3 software is bundled with the BSC9131NXE1KHKB silicon; licensing and integration are handled separately per customer agreement.
BSC9131NXE1KHKB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 520-FBGA, FCBGA
- Series:
- QorIQ Qonverge BSC
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- PowerPC e500
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 800MHz
- Co-Processors/DSP:
- Signal Processing; SC3850, Security; SEC 4.4
- RAM Controllers:
- DDR3, DDR3L
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- -
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 (1)
- Voltage - I/O:
- 1.8V, 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- Boot Security, Cryptography, Random Number Generator
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 520-FCBGA (21x21)
- Additional Interfaces:
- AIC, DUART, I2C, MMC/SD, SPI, USIM
BSC9131NXE1KHKB FAQ
1.How can I place an order for BSC9131NXE1KHKB through Aetrix?
Please submit a Request for Quotation (RFQ) for BSC9131NXE1KHKB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for BSC9131NXE1KHKB reliable?
The price and inventory of BSC9131NXE1KHKB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for BSC9131NXE1KHKB is usually 5 days.
3.What payment methods are accepted for BSC9131NXE1KHKB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for BSC9131NXE1KHKB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for BSC9131NXE1KHKB?
BSC9131NXE1KHKB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your BSC9131NXE1KHKB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for BSC9131NXE1KHKB?
For technical support, including BSC9131NXE1KHKB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your BSC9131NXE1KHKB requirements.
6.How does Aetrix verify that BSC9131NXE1KHKB is sourced from the original manufacturer or authorized distributors?
All BSC9131NXE1KHKB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that BSC9131NXE1KHKB meets industry standards.
7.What is the process for return or replacement of BSC9131NXE1KHKB?
All BSC9131NXE1KHKB units undergo pre-shipment inspection (PSI). If there is an issue with BSC9131NXE1KHKB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The BSC9131NXE1KHKB part is unused and in its original packaging.
Return procedure for BSC9131NXE1KHKB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
BSC9131NXE1KHKB Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

