Texas Instruments BUF802IRGTR
- Part No.:
- BUF802IRGTR
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 16-VFQFN Exposed Pad
- Datasheet:
-
BUF802IRGTR.pdf
- Description:
- WIDE-BANDWIDTH, 2.3-NV/HZ, JFET
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
BUF802IRGTR from Texas Instruments is a wide-bandwidth, high-input-impedance JFET-input buffer IC designed for front-end signal conditioning in high-frequency data acquisition systems. It delivers 3.1GHz large-signal bandwidth, 7000V/µs slew rate, and 2.3nV/√Hz input voltage noise while driving 50Ω loads - enabling use in oscilloscope front-ends and active probe interfaces.
For engineers reviewing the BUF802IRGTR datasheet, BUF802IRGTR pinout, BUF802IRGTR application, or BUF802IRGTR equivalent, key selection considerations include its dual-mode operation (Buffer Mode and Composite Loop Mode), adjustable quiescent current via R_Bias, integrated input/output clamping with sub-nanosecond recovery, and ±4.5V to ±6.5V dual-supply support.
Technical Context
The BUF802IRGTR implements an open-loop, unity-gain architecture with a low-noise JFET input stage and a diamond-buffer output stage optimized for 50Ω/100Ω drive. Its functional block includes three distinct sections: input stage (JFET + biasing), clamp stage (bidirectional diode clamps on IN/OUT), and output stage (high-current, low-Z driver).
It operates in two configurable modes: Buffer Mode (BF) for standalone wideband buffering, and Composite Loop Mode (CL) where In_Aux enables closed-loop control with an external precision amplifier to achieve DC accuracy without sacrificing AC performance. Pin functionality (e.g., CLH/CLL, R_Bias, In_Aux) is mode-dependent and explicitly defined per mode in the datasheet.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Large-signal bandwidth | 3.1GHz at 1VPP - supports full-scale transient capture in GHz-class oscilloscope front-ends without distortion-induced aliasing. |
| Slew rate | 7000V/µs - enables faithful reproduction of fast-rising edges (e.g., <0.16ns rise time) in high-speed test equipment. |
| Input voltage noise | 2.3nV/√Hz at 100MHz - preserves SNR in low-amplitude, high-frequency signal chains such as NDT receivers. |
| Input impedance | 50GΩ || 2.4pF at 100MHz - minimizes loading on high-Z sources like passive probes and piezoelectric sensors. |
| Clamp recovery time | 0.2ns (CLH/CLL) - ensures rapid return from overdrive in burst-mode or pulse-based acquisition systems. |
| Quiescent current range | 21–37mA (adjustable via R_Bias) - allows trade-off between power (e.g., 21mA in Low IQ mode) and distortion (e.g., –45dBc HD2 at 2GHz in Wide BW mode). |
| Supply voltage | ±4.5V to ±6.5V - supports standard ±5V and ±6V lab-grade supply rails while maintaining rail-to-rail output swing. |
Pinout & Package
The BUF802IRGTR is housed in a 3mm × 3mm, 16-pin VQFN package (RGT) with exposed thermal pad. The package supports high-density PCB layouts and efficient thermal dissipation (RθJB = 27°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN (Pin 2) | Main signal input | High-impedance JFET gate node; primary path for wideband signal routing in BF mode. |
| OUT (Pin 11) | Main signal output | Low-impedance diamond-buffer output capable of sourcing/sinking >100mA into 50Ω loads. |
| R_Bias (Pin 7) | Output-stage bias current control | Resistor-connected pin setting quiescent current (21–37mA); determines bandwidth/distortion/power trade-off. |
| CLH (Pin 15) / CLL (Pin 14) | Output clamp voltage reference | Set positive/negative output voltage limits; define safe swing boundaries for downstream 5V-process amplifiers. |
| VSO+ (Pin 12) / VSO– (Pin 10) | Output-stage power supply | Separate supply pins for output stage; internally connected to VS+ and VS– via back-to-back diodes. |
| VS+ (Pin 1) / VS– (Pins 5, 8) | Input-stage power supply | Dual-supply inputs for JFET stage; pins 5 and 8 are internally shorted for robust grounding. |
| In_Aux (Pin 4) | Auxiliary control input | Enables composite loop operation; provides gain of 6.15V/V at DC and 800MHz bandwidth for precision feedback path. |
| NC (Pins 9, 13, 16) | No-connect | Must remain unconnected; no internal connection or function. |
Key Features
| Feature | Design Value |
|---|---|
| Adjustable quiescent current | R_Bias resistor sets IQ from 21mA (Low IQ mode, 2GHz LSBW) to 37mA (Wide BW mode, 3.1GHz LSBW), enabling system-level power/performance tuning. |
| Integrated input/output clamping | Sub-0.3ns clamp activation protects both the BUF802IRGTR's JFET input and downstream 5V VGAs from overvoltage transients during probing or fault events. |
| Dual operational modes | Buffer Mode (standalone 3.1GHz buffer) and Composite Loop Mode (In_Aux + external op-amp for DC precision + AC bandwidth synergy) - no hardware change required. |
| High-Z, low-noise input stage | 50GΩ || 2.4pF input impedance and 2.3nV/√Hz noise floor preserve signal integrity from ultra-high-impedance sources (e.g., piezoelectric sensors, passive probes). |
| 50Ω load drive capability | Output stage delivers >100mA into 50Ω while maintaining <0.7ns 1% settling time - eliminates need for external line drivers in T&M instrument designs. |
Applications
| Oscilloscope Front-End | Active Probe Interface |
|---|---|
|
Use Scenario: Signal conditioning stage before ADC in 1–4GHz real-time oscilloscopes. IC Role / Device Role / Timing Role: High-fidelity, low-loading buffer isolating passive probe tip from sampling circuitry. Use Value: 3.1GHz bandwidth and 0.7ns 1% settling enable accurate capture of multi-GHz edge transitions without amplitude droop or ringing. |
Use Scenario: Input buffer in compact, high-bandwidth active differential probes. IC Role / Device Role / Timing Role: First-stage buffer converting high-Z probe tip signal to low-Z, 50Ω-compatible output. Use Value: 50GΩ || 2.4pF input impedance prevents probe tip loading; 7000V/µs slew rate preserves fast edge fidelity over full dynamic range. |
| Nondestructive Testing (NDT) | High-Frequency Data Acquisition |
|
Use Scenario: Receiver front-end in ultrasonic or eddy-current NDT systems operating up to 2GHz. IC Role / Device Role / Timing Role: Low-noise, high-Z amplifier buffer for piezoelectric transducer signals. Use Value: 2.3nV/√Hz input noise and sub-1ns settling minimize SNR degradation in weak, high-frequency echo detection. |
Use Scenario: Analog front-end buffer in modular digitizers and RF sampling systems. IC Role / Device Role / Timing Role: Wideband unity-gain driver between anti-alias filter and ADC input. Use Value: 3.1GHz SSBW and 50Ω drive capability ensure flat frequency response and impedance-matched signal transfer to high-speed ADCs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-bandwidth buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMH6723MA/NOPB | 2.8GHz GBW, 5.5kV/µs slew rate, 3.9nV/√Hz noise, fixed 12mA IQ, SOIC-8 package. | Lacks adjustable IQ, integrated clamping, and Composite Loop Mode; limited to standalone buffering. | Choose when board space permits SOIC-8 and lower noise floor is not critical; avoid for clamp-protected or power-tunable designs. |
| THS4304DR | 1.8GHz GBW, 4.2kV/µs slew rate, 2.5nV/√Hz noise, 20mA IQ, SOIC-8 package. | No input/output clamping, no auxiliary control path, no JFET input - higher input bias current (2µA vs 3pA). | Use only in non-overvoltage-prone environments requiring moderate bandwidth; unsuitable for active probe or oscilloscope front-end safety-critical paths. |
Compared with LMH6723MA/NOPB and THS4304DR, the BUF802IRGTR uniquely combines GHz-class bandwidth, sub-pA input bias, integrated clamping, and dual-mode operation - making it the only option supporting both ultra-low-noise acquisition and robust overvoltage protection in a single 3mm × 3mm package.
Availability
BUF802IRGTR is available at Aetrix Electronics and suitable for oscilloscope front-ends, active probe interfaces, and high-frequency data acquisition systems requiring stable component supply, long-term production continuity, and traceable sourcing.
Supply support for BUF802IRGTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance signal chain solutions with decades of expertise in precision and high-speed amplification.
The BUF802IRGTR belongs to TI's high-speed buffer product line, engineered specifically for GHz-bandwidth, low-noise, high-input-impedance signal acquisition in test & measurement, medical imaging, and communications infrastructure.
FAQ
What is the primary circuit role of the BUF802IRGTR in a signal chain?
The BUF802IRGTR serves as a high-input-impedance, wideband unity-gain buffer - primarily placed at the front-end of data acquisition systems to isolate sensitive sources (e.g., passive probes, piezoelectric sensors) from downstream circuitry while preserving signal fidelity up to 3.1GHz. Its JFET input stage and diamond-buffer output make the BUF802IRGTR ideal for applications demanding minimal loading and robust 50Ω drive capability.
How does the R_Bias pin affect performance of the BUF802IRGTR?
The R_Bias pin (Pin 7) sets the output-stage quiescent current by connecting an external resistor to VS–; typical values are 17.8kΩ (37mA, Wide BW mode) or 35.7kΩ (24mA, Low IQ mode). This adjustment directly trades off bandwidth (3.1GHz → 2GHz), slew rate (7000V/µs → 5500V/µs), and harmonic distortion (–45dBc → –56dBc at 1GHz), allowing system-level optimization of the BUF802IRGTR for power-constrained or performance-critical designs.
Can the BUF802IRGTR operate in single-supply configurations?
Yes - the BUF802IRGTR supports single-supply operation from 9V to 13V (e.g., +12V and GND), as specified in Section 5.3 Recommended Operating Conditions. However, the input common-mode range and output swing become asymmetric, and CLH/CLL clamp references must be re-biased accordingly. For optimal performance and symmetric clipping behavior, dual-supply operation (±4.5V to ±6.5V) is recommended and validated across all electrical characteristics tables for the BUF802IRGTR.
What is the function of the In_Aux pin on the BUF802IRGTR?
The In_Aux pin (Pin 4) enables Composite Loop Mode (CL Mode), where an external precision amplifier controls the BUF802IRGTR's output via feedback - combining the BUF802IRGTR's GHz bandwidth with the op-amp's DC accuracy. In this configuration, In_Aux provides 6.15V/V gain at DC and 800MHz bandwidth, allowing high-precision, wideband signal conditioning without sacrificing settling time or noise performance inherent to the BUF802IRGTR.
Does the BUF802IRGTR require external clamping components?
No - the BUF802IRGTR integrates bidirectional input and output clamp diodes (rated for 100mA continuous) controlled by CLH and CLL pins. When CLH and CLL are tied to VS+ and VS– respectively, internal clamping is active with 0.2ns response. External clamps are optional and only needed if transient currents exceed 100mA; in that case, internal clamps are disabled by connecting CLH/CLL to VS+/VS–, and external diodes are added - a configuration fully supported in the BUF802IRGTR's design guidelines.
BUF802IRGTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Amplifier Type:
- J-FET
- Number of Circuits:
- 1
- Output Type:
- Push-Pull
- Slew Rate:
- 7000V/µs
- Gain Bandwidth Product:
- -
- -3db Bandwidth:
- 3.1 GHz
- Current - Input Bias:
- 7 pA
- Voltage - Input Offset:
- 600 mV
- Current - Supply:
- 34mA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 9 V
- Voltage - Supply Span (Max):
- 13 V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-VQFN (3x3)
BUF802IRGTR FAQ
1.How can I place an order for BUF802IRGTR through Aetrix?
Please submit a Request for Quotation (RFQ) for BUF802IRGTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for BUF802IRGTR reliable?
The price and inventory of BUF802IRGTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for BUF802IRGTR is usually 5 days.
3.What payment methods are accepted for BUF802IRGTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for BUF802IRGTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for BUF802IRGTR?
BUF802IRGTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your BUF802IRGTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for BUF802IRGTR?
For technical support, including BUF802IRGTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your BUF802IRGTR requirements.
6.How does Aetrix verify that BUF802IRGTR is sourced from the original manufacturer or authorized distributors?
All BUF802IRGTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that BUF802IRGTR meets industry standards.
7.What is the process for return or replacement of BUF802IRGTR?
All BUF802IRGTR units undergo pre-shipment inspection (PSI). If there is an issue with BUF802IRGTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The BUF802IRGTR part is unused and in its original packaging.
Return procedure for BUF802IRGTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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